Patents by Inventor Takashi Yokoyama

Takashi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6100580
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6099945
    Abstract: There is provided a method of patterning a substrate with an atomic mask having a mask substrate and first atoms adsorbed on the mask substrate, the first atoms forming a mask pattern having a one-atomic thickness, including the steps, in sequence, of (a) depositing adatoms over a surface of a substrate to be patterned, the adatoms having low reactivity with second atoms of which the substrate is composed, and (b) placed the atomic mask close to the substrate in such a distance that the first atoms form a chemical bond with the adatoms, so that adatoms located nearest to the first atoms are desorbed out of the substrate to form a pattern on the substrate, the pattern being defined as an area where none of the adatoms exists. In accordance with the above mentioned method, it is possible to form a pattern on the sub-nanometer or nanometer order with high accuracy and in a short period of time, and it is also possible to repeatedly form the same pattern by using the atomic mask.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Masakazu Baba
  • Patent number: 6081023
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: June 27, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6072231
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: June 6, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6069029
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: May 30, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6049534
    Abstract: A communication system includes a control unit, a switch and a diversity hand-over processing unit connected to the control unit and the switch for receiving, both a first communication signal received from a radio base station which outputs the hand-over instruction, and a second communication signal which receives it from another radio base station to which the communication signal will be hand-over to output one of the first and second communication signals to the associated interface circuit, and for transmitting the communication signal received through the radio base station from the mobile station on the reception side for communication to both the interface circuit associated with the radio base station as a source of hand-over and the interface circuit associated with the radio base station as a destination of hand-over.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: April 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Sakamoto, Tsutomu Kusaki, Masaru Murakami, Takashi Yokoyama
  • Patent number: 6049091
    Abstract: There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having an electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween. The above mentioned field effect transistor utilizes a difference in electron affinity between the amorphous semiconductor layer and the semiconductor layer to thereby make it possible to operate at a higher speed because carriers are not influenced by scattering of doped ions.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: April 11, 2000
    Assignee: NEC Corporation
    Inventor: Takashi Yokoyama
  • Patent number: 6030450
    Abstract: The cooling speed of the portion near the rear part of a single-crystal body and passing through the defect-forming temperature zone is kept the same as that of the front portion of the single-crystal body. Namely, the heater is kept in operation while pulling the single crystal silicon subsequent to forming the tail of the single crystal silicon and the cooling speed throughout the whole single-crystal body in the defect-forming temperature zone is kept below 15.degree. C./min (levels A and B). Furthermore, the length of the tail is preset in the process of pulling the single crystal silicon so that the single-crystal body cools down slowly while passing through the defect-forming temperature zone (level C).
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: February 29, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshiaki Saishouji, Takashi Yokoyama, Hirotaka Nakajima, Toshimichi Kubota, Kouzou Nakamura
  • Patent number: 6019106
    Abstract: A cigarette has a shredded tobacco filler and a paper for wrapping the filler. Many frusto-pyramidal portions biting into the filler are formed so as to be distributed on an inner surface of the paper except on both of the side edge portions of the inner surface. The inner surface, so formed, provides a high coefficient of friction with respect to the shredded tobacco filler. This cigarette contributes to preventing the dropping of shredded tobacco from the cut end of the cigarette.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: February 1, 2000
    Assignee: Japan Tobacco Inc.
    Inventors: Toshiaki Okusawa, Shichisei Tani, Takashi Koyama, Takashi Yokoyama
  • Patent number: 6018191
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: January 25, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 5988602
    Abstract: A variable venturi carburetor, which is part of an intake system of an internal combustion engine, includes structural features which allow an air intake path of the carburetor to be shortened, and which allow the size of air chambers of the carburetor to be reduced. A piston valve is composed of a plate-shaped valve and a tubular portion. The plate-shaped valve is guided by a pair of grooves provide in sidewalls of the intake path. The tubular portion is attached to one side of the plate-shaped valve near a center of the side of the plate-shaped valve. The tubular portion has a rectangular or square cross-section. Each side of the rectangular cross section is shorter than the internal diameter of the intake path. A flange is attached to an upper end of the piston valve. The flange is of a reduced diameter and facilitates connection of the piston valve to a diaphragm.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: November 23, 1999
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Takashi Yokoyama, Takashi Udono
  • Patent number: 5981315
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: November 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 5972795
    Abstract: A method and an apparatus for producing a wafer from a crystalline ingot, wherein the method supplies an etching gas, having a high etching property for at least one constituent of the crystalline ingot, in a state of a molecular beam stream on a predetermined part of the crystalline ingot to be processed, volatilizing the predetermined part gradually from the ingot, and then removing the predetermined part entirely so as to cut the wafer from the ingot. According to the method, waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: October 26, 1999
    Assignee: Daido Hoxan Inc.
    Inventors: Takashi Yokoyama, Kazuma Yamamoto, Masato Yamamoto, Takahiro Mishima, Go Matsuda, Shigeki Itou
  • Patent number: 5931676
    Abstract: A dental magnetic attachment, which is embedded in the denture base so as to face a soft magnetic keeper 103 and attract the keeper by magnetic force, comprising at least three yokes which are plates and made of soft magnetic material, and at least two pieces of magnet which have the magnetization direction parallel to the thickness. In the example the attachment comprises a central yoke 10, the magnet 1, the magnet 2, the outer yoke 11, and the outer yoke 12. The invention is characterized by a magnet arrangement in which like poles of the magnet 1 and the magnet 2 faces each other. Because of it mutually independent two magnetic circuits are formed and they offer strong attractive force which is two times larger than that of existing ones in a compact volume required for dental attachment.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: August 3, 1999
    Assignee: Aichi Steel Works, Ltd.
    Inventors: Yoshinobu Honkura, Takashi Yokoyama, Hideki Fujii, Yoshinobu Tanaka
  • Patent number: 5927159
    Abstract: A ratchet wrench including a fixed jaw and a movable jaw attached to a body of the ratchet wrench and having V-shaped nut gripping portions opposing each other. The fixed jaw is pivoted to a forward end portion of the body and biased to rotate toward the movable jaw by a spring. An adjusting nut is provided rotatably about a longitudinal center axis of the body, and an adjusting screw rod is threaded into the adjusting nut so that it is movable back and forth along the longitudinal center axis of the body by rotating the adjusting nut in one direction or the other. The movable jaw is pivoted at a rear end portion thereof to the adjusting screw rod by a guide pin which is guided along a longitudinal slot provided in the body and, the movable jaw is biased to rotate toward the fixed jaw by a spring provided between the movable jaw and the adjusting screw rod.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: July 27, 1999
    Assignee: MCC Corporation
    Inventors: Takashi Yokoyama, Akihiro Yamakado
  • Patent number: 5914530
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: June 22, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 5912186
    Abstract: A method for processing semiconductor materials such as a crystalline ingot or a wafer and an apparatus employed therein. An etching gas is supplied on the surface of a semiconductor material, while laser irradiation or light quantum irradiation is applied on a predetermined part of the semiconductor material surface, whereby a component of the etching gas is excited, reacted with a component of the semiconductor material and evaporated for elimination. Thereby, semiconductor materials can be processed hygienically, easily and with high precision.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: June 15, 1999
    Assignee: Daido Hoxan, Inc.
    Inventors: Akira Yoshino, Takashi Yokoyama, Yoshinori Ohmori, Kazuma Yamamoto
  • Patent number: 5880926
    Abstract: An electrolytic capacitor device includes a capacitor which has a capacitor element and leads extending from one end of the element, and a square mounting board for use in mounting the capacitor device on a printed circuit board. The mounting board is connected to the one end of the capacitor. The leads are inserted into openings extending through the mounting board. The mounting board has parallel slits extending from the openings to one side edge of the mounting board. Each slit is wider in its open end at the one side edge of the mounting board than the diameter of the associated opening. The bottom surface of the mounting board has metal plate terminals which extend from the openings to different side edges of the mounting board. The terminals have rising portions extending upward along the inner walls of the slits and the openings. The leads have tip ends welded in their peripheries to the rising portions. The top surface of the mounting board has a U-shaped stop opening toward the one side edge.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: March 9, 1999
    Assignee: Nichicon Corporation
    Inventors: Seiichi Nishino, Kozaburo Okubo, Hiroyuki Nakagawa, Takashi Yokoyama, Takeru Nonoguchi
  • Patent number: 5863817
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: January 26, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 5821606
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: October 13, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto