Patents by Inventor Takashi Yokoyama

Takashi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6287956
    Abstract: A multilevel interconnecting structure includes a plurality of interconnecting layers formed on a semiconductor substrate, a fluorine-doped oxide film for burying portions between the interconnecting layers, and an oxide film formed on the fluorine-doped oxide film, having a planarized surface, and not containing fluorine. A method of forming the multilevel interconnecting structure is also disclosed.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Yoshiaki Yamada, Koji Kishimoto
  • Patent number: 6289008
    Abstract: A communication system includes a control unit, a switch and a diversity hand-over processing unit connected to the control unit and the switch for receiving, both a first communication signal received from a radio base station which outputs the hand-over instruction, and a second communication signal which receives it from another radio base station to which the communication signal will be hand-over to output one of the first and second communication signals to the associated interface circuit, and for transmitting the communication signal received through the radio base station from the mobile station on the reception side for communication to both the interface circuit associated with the radio base station as a source of hand-over and the interface circuit associated with the radio base station as a destination of hand-over.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: September 11, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Sakamoto, Tsutomu Kusaki, Masaru Murakami, Takashi Yokoyama
  • Publication number: 20010019957
    Abstract: In a mobile communication system having an ATM-processed transfer path, a non-instantaneous interrupt handover can be realized. In a mobile communication network including an ATM-processed transfer path, when a mobile station is moved between cells during communication, frames are received to be identified by a mobile switching center. The frames contain the same data received from both base stations covering the cell range at asynchronous timing different from each other. A selection is made of header information with the lowest error rate from the header information of these frames. The frames are connected at instructed timing. Also, the frames to be transmitted to a plurality of base stations are duplicated, and then transmission timing is specified from these header information. These duplicated frames are transmitted at the specified transmission timing, so that the non-instantaneous interrupt handover is carried out.
    Type: Application
    Filed: May 14, 2001
    Publication date: September 6, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Tsutomu Kusaki, Kenichi Sakamoto, Masaru Murakami, Takashi Yokoyama
  • Publication number: 20010019857
    Abstract: An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—H bond or a Si-CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.
    Type: Application
    Filed: January 23, 2001
    Publication date: September 6, 2001
    Inventors: Takashi Yokoyama, Tatsuya Usami
  • Patent number: 6284661
    Abstract: A method and an apparatus for cutting a wafer from a crystalline ingot, by directing a stream or streams of etching gas at the crystalline ingot in a vacuum. Waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: September 4, 2001
    Assignee: Daido Hoxan Inc.
    Inventors: Takashi Yokoyama, Kazuma Yamamoto, Masato Yamamoto, Takahiro Mishima, Go Matsuda, Shigeki Itou
  • Patent number: 6281445
    Abstract: A connection device for use in connection between two electronic components and a connection device provided on a first electronic component. The connection device includes two metal layers which have mutually different coefficients of thermal expansion, and a plurality of side wall pieces that are provided on the metal layers so as to form a connecting space for a second electronic component.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: August 28, 2001
    Assignee: NEC Corporation
    Inventor: Takashi Yokoyama
  • Publication number: 20010008302
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: January 30, 2001
    Publication date: July 19, 2001
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6263204
    Abstract: In a mobile communication system having an ATM-processed transfer path, a non-instantaneous interrupt handover can be realized. In a mobile communication network including an ATM-processed transfer path, when a mobile station is moved between cells during communication, frames are received to be identified by a mobile switching center. The frames contain the same data received from both base stations covering the cell range at asynchronous timing different from each other. A selection is made of header information with the lowest error rate from the header information of these frames. The frames are connected at instructed timing. Also, the frames to be transmitted to a plurality of base stations are duplicated, and then transmission timing is specified from these header information. These duplicated frames are transmitted at the specified transmission timing, so that the non-instantaneous interrupt handover is carried out.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: July 17, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Kusaki, Kenichi Sakamoto, Masaru Murakami, Takashi Yokoyama
  • Patent number: 6259920
    Abstract: In a mobile communication system having an ATM-processed transfer path, a non-instantaneous interrupt handover can be realized. In a mobile communication network including an ATM-processed transfer path, when a mobile station is moved between cells during communication, frames are received to be identified by a mobile switching center. The frames contain the same data received from both base stations covering the cell range at asynchronous timing different from each other. A selection is made of header information with the lowest error rate from the header information of these frames. The frames are connected at instructed timing. Also, the frames to be transmitted to a plurality of base stations are duplicated, and then transmission timing is specified from these header information. These duplicated frames are transmitted at the specified transmission timing, so that the non-instantaneous interrupt handover is carried out.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: July 10, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Kusaki, Kenichi Sakamoto, Masaru Murakami, Takashi Yokoyama
  • Patent number: 6255732
    Abstract: An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—H bond or a Si—CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: July 3, 2001
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Tatsuya Usami
  • Patent number: 6245665
    Abstract: A semiconductor device equipped with the dual damascene structure that is provided, which suppresses the propagation delay of signals effectively without using any complicated processes.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: June 12, 2001
    Assignee: NEC Corporation
    Inventor: Takashi Yokoyama
  • Patent number: 6225196
    Abstract: There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween. The above mentioned field effect transistor utilizes a difference in electron affinity between the amorphous semiconductor layer and the semiconductor layer to thereby make it possible to operate at a higher speed because carriers are not influenced by scattering of doped ions.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: May 1, 2001
    Assignee: NEC Corporation
    Inventor: Takashi Yokoyama
  • Patent number: 6204552
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6189461
    Abstract: An incineration apparatus which can suppress the generation of dioxins, including a combustion furnace (11) for burning a combustible in combustion air within the furnace, chlorinated aromatic compound measuring device (12) for measuring an amount of a chlorinated aromatic compound generated in the combustion furnace, and control device (14, 15, 16) for monitoring the amount of the chlorinated aromatic compound generated, obtained by the measuring device (12), and varying operating conditions of the combustion furnace (11) on the basis of the monitored result, such as to decrease the amount of the chlorinated aromatic compound generated in the combustion furnace (11).
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: February 20, 2001
    Assignee: NKK Corporation
    Inventors: Kunio Miyazawa, Hideki Nagano, Satoshi Fujii, Manabu Kuroda, Takashi Yokoyama, Takaaki Kondo
  • Patent number: 6179910
    Abstract: This invention provides a method for manufacturing silicon single crystals. The method is capable of eliminating void defects existing in deep regions of a silicon single crystal despite the size of the silicon single crystal. The silicon single crystals according to this invention are pulled the radius of a ring-shaped oxidation induced stacking fault (OSF ring) of a wafer is larger than half the radius of the wafer during the process of thermal oxidation treatment.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: January 30, 2001
    Assignee: Komatsu Electronic Metals Co., LTD
    Inventors: Takashi Yokoyama, Shin Matsukuma, Toshiaki Saishoji, Kozo Nakamura, Junsuke Tomioka
  • Patent number: 6130114
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: October 10, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 6130154
    Abstract: A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: October 10, 2000
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Yoshiaki Yamada, Koji Kishimoto
  • Patent number: 6124629
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: September 26, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6108546
    Abstract: In a mobile communication system having an ATM-processed transfer path, a non-instantaneous interrupt handover can be realized. In a mobile communication network including an ATM-processed transfer path, when a mobile station is moved between cells during communication, frames are received to be identified by a mobile switching center. The frames contain the same data received from both base stations covering the cell range at asynchronous timing different from each other. A selection is made of header information with the lowest error rate from the header information of these frames. The frames are connected at instructed timing. Also, the frames to be transmitted to a plurality of base stations are duplicated, and then transmission timing is specified from these header information. These duplicated frames are transmitted at the specified transmission timing, so that the non-instantaneous interrupt handover is carried out.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Kusaki, Kenichi Sakamoto, Masaru Murakami, Takashi Yokoyama
  • Patent number: 6100580
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto