Abstract: A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.

Abstract: A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.

Abstract: A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.

Abstract: A method for decreasing the concentration of a chlorinated aromatic compound in the exhaust gas from a combustion furnace. The exhaust gas from the combustion furnace is passed through a bag filter. The concentration of the chlorinated aromatic compound in the exhaust gas is measured and the operating temperature of the bag filter is adjusted based on the measured concentration of the chlorinated aromatic compound in order to decrease the concentration of the chlorinated aromatic compound in the exhaust gas.

Abstract: A material 1 to be shaped is reduced and formed by bringing dies with convex forming surfaces, when viewed from the side of the transfer line of the material 1, close to the transfer line from above and below the material 1, in synchronism with each other, while giving the dies a swinging motion in such a manner that the portions of the forming surfaces of the dies, in contact with the material 1, are transferred from the upstream to the downstream side in the direction of the transfer line.

Abstract: In an electric throttle-control apparatus for controlling an open position of a throttle valve 6 connected to reduction gears 47 to reduce rotational speed of the motor 4, by driving a motor 4 which includes a commutator 32 with a plurality of slots 44, and brushes 31 and 31′, the number of the slots in the commutator and the arrangement of brushes on the slots are set such that even and odd number slot states appear alternately in an electrical equivalent-circuit of a wire-connection among slots including the brushes while the motor rotates. Further, if the number of the slots 44 is the odd number 9, 11, or 13, the brushes 31 and 31′ are arranged in a 180° opposed placement, and if the number of the slots 44 is the even number 10 or 12, the brushes 31 and 31′ are arranged in a non-opposed placement shifted from a 180° opposed placement.

Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Abstract: A semiconductor device and a manufacturing method thereof which enable corrosion of an Al-wiring to be prevented in the case where insulating film containing fluorine is in use. Al-wiring is formed on a silicon substrate, while etching Aluminum with photoresist as a mask. In this process, a natural oxide film is formed on side wall of the Al-wiring. There is eliminated the natural oxide film by physical etching due to inert gas such as argon and so forth or reactive etching such as BCl3 and so forth under atmosphere of reduced pressure or a few existence of oxygen. In succession, there is formed high quality aluminum oxide film 6a on the Al-side wall, while introducing oxygen or oxygen radical in a state of not breaking a vacuum. There is formed a fluorine contained interlayer insulating film 7 on a barrier of high quality aluminum oxide film 6a.

Abstract: A sputtering method of depositing a titanium nitride film on a titanium film in contact with a silicon at a bottom of a contact hole is provided, wherein the sputtering method is carried out at a temperature of the silicon region of not less than 450° C., so that the titanium nitride film has a compressive stress of not higher than 5×109 dyne/cm2 whereby the titanium film has such a high stability as preventing any crack upon changing the compressive stress to a tensile stress by a heat treatment.

Abstract: A sputtering method of depositing a titanium nitride film on a titanium film in contact with a silicon at a bottom of a contact hole is provided, wherein the sputtering method is carried out at a temperature of the silicon region of not less than 450° C., so that the titanium nitride film has a compressive stress of not higher than 5×109 dyne/cm2 whereby the titanium film has such a high stability as preventing any crack upon changing the compressive stress to a tensile stress by a heat treatment.

Abstract: A material 1 to be shaped is reduced and formed by bringing dies with convex forming surfaces, when viewed from the side of the transfer line of the material 1, close to the transfer line from above and below the material 1, in synchronism with each other, while giving the dies a swinging motion in such a manner that the portions of the forming surfaces of the dies, in contact with the material 1, are transferred from the upstream to the downstream side in the direction of the transfer line.

Abstract: There is provided a method of patterning a substrate with an atomic mask having a mask substrate and first atoms adsorbed on the mask substrate, the first atoms forming a mask pattern having a one-atomic thickness, including the steps, in sequence, of (a) depositing adatoms over a surface of a substrate to be patterned, the adatoms having low reactivity with second atoms of which the substrate is composed, and (b) putting the atomic mask close to the substrate in such a distance that the first atoms make a chemical bond with the adatoms, so that adatoms located nearest to the first atoms are desorbed out of the substrate to form a pattern on the substrate, the pattern being defined as an area where none of the adatoms exists. In accordance with the above mentioned method, it is possible to form a pattern on the sub-nanometer or nanometer order with high accuracy and in a short period of time, and it is also possible to repeatedly form the same pattern by using the atomic mask.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: The multilayer wiring structure for a semiconductor device according to the present invention is constituted by including a semiconductor substrate, a copper wiring covered with a diffusion preventive film, formed on the semiconductor substrate, a first layer insulating film formed on the semiconductor substrate and the copper wiring, a second layer insulating film with lower permittivity than that of the first layer insulating film formed on the first layer insulating film, a connection hole formed in the first layer insulating film and the second layer insulating film exposing the copper wiring to the hole, a groove formed in the second layer insulating film with its bottom making contact with the connection hole, a barrier metal layer formed on the side face of the connection hole and the groove, a copper via filling in the interior of the connection hole, and a copper groove wiring filling in the interior of the groove.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A method for producing a semiconductor device of the present invention includes the steps of: forming an interlayer insulation film on a semiconductor substrate; forming a groove in the interlayer insulation film; forming a metal interconnect layer in the groove; forming an oxidization-resistant metal layer on an upper surface of the metal interconnect layer by an electroless plating method; and forming an oxygen-containing insulation film on an upper surface of the metal layer.

Abstract: A hot water type first idle control device includes a heating chamber through which cooling water for an engine is allowed to flow, a wax case heated by the heating chamber, and a device housing in which the wax case is accommodated and retained. In the hot water type first idle control device, the heating chamber is integrally defined in the device housing to adjoin the wax case with a partition wall interposed therebetween for separating the heating chamber from the inside of the device housing. Thus, it is possible to effectively heat the wax case by hot water, while preventing the entering of the hot water into the device housing.

Abstract: A Cu wiring is formed on a higher layer than a Si substrate, and a via plug formed in a via hole communicates with the higher layer and the Si substrate. Etch rates of a HSQ layer surrounding a damascene and the first SiO2 layer formed on the Si substrate change in different modes depending on the ratio of the flow rate of the first reactive gas to that of the second reactive gas. According to the aforementioned structure, a dual damascene structure of the semiconductor device in which there is no necessity for forming a stopper layer formed of silicon nitride between the insulating layers, and a capacitance between wirings can be reduced.

Abstract: The present invention is directed to a process for manufacturing a semiconductor device. It includes a step for forming a fine wiring, and provides a process for uniformly and positively forming a film of a barrier metal, such as tantalum, for preventing the metal, such as copper, which becomes the first material for the wiring, from diffusing into a silicon oxide film. The process involves depositing an oxide of a barrier metal on a substrate which is formed with a via hole by a process such as CVD process. A high quality barrier metal film is formed by reducing the oxide by applying a negative potential to the oxide in a solution in which hydrogen ions are present. Subsequently an embedded wiring is formed by embedding the main metal by a plating process and the like and polishing to remove unnecessary portions.

Abstract: A semiconductor device equipped with the dual damascene structure that is provided, which suppresses the propagation delay of signals effectively without using any complicated processes.