Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: In a mobile communication system having an ATM-processed transfer path, a non-instantaneous interrupt handover can be realized. In a mobile communication network including an ATM-processed transfer path, when a mobile station is moved between cells during communication, frames are received to be identified by a mobile switching center. The frames contain the same data received from both base stations covering the cell range at asynchronous timing different from each other. A selection is made of header information with the lowest error rate from the header information of these frames. The frames are connected at instructed timing. Also, the frames to be transmitted to a plurality of base stations are duplicated, and then transmission timing is specified from these header information. These duplicated frames are transmitted at the specified transmission timing, so that the non-instantaneous interrupt handover is carried out.

Abstract: A seat device adapted to be fixed to engagement members on a vehicle floor includes a first engagement member supporting a front portion of the seat device, a second engagement member supporting a rear portion of the seat, a first lock engagable with the first engagement member, a second lock engagable with the second engagement member. The first lock is supported on the seat device and includes a bracket rotatably supported relative to the seat device and being engagable with the first engagement member and a hook member supported on the bracket and being able to maintain an engagement of the bracket with the first engagement member. A contact portion is provided on the hook member for contacting on a portion of the seat device to prevent a release operation of the hook member when the bracket is out of a predetermined position range relative to the seat device.

Abstract: A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A material 1 to be shaped is reduced and formed by bringing dies with convex forming surfaces, when viewed from the side of the transfer line of the material 1, close to the transfer line from above and below the material 1, in synchronism with each other, while giving the dies a swinging motion in such a manner that the portions of the forming surfaces of the dies, in contact with the material 1, are transferred from the upstream to the downstream side in the direction of the transfer line.

Abstract: A material 1 to be shaped is reduced and formed by bringing dies with convex forming surfaces, when viewed from the side of the transfer line of the material 1, close to the transfer line from above and below the material 1, in synchronism with each other, while giving the dies a swinging motion in such a manner that the portions of the forming surfaces of the dies, in contact with the material 1, are transferred from the upstream to the downstream side in the direction of the transfer line.

Abstract: A semiconductor device with satisfactory bonding ability of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for burying wiring space portions. The semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is formed by etching the anti-reflection layer and the metal layer while taking the patterned insulation layer as a mask and leaving the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface thereby.

Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and memory cells each constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein the memory cells are disposed in series, and the island-like semiconductor layer on which the memory cells are disposed has cross-sectional areas in a horizontal direction which vary stepwise.

Abstract: A semiconductor device with dual damascene structure is provided, which suppresses propagation delay of signals without using complicated processes. The device comprises a semiconductor substrate having a lower wiring layer and electronic elements, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer made of carbon-containing SiO2, a third dielectric layer on the second dielectric layer, a fourth dielectric layer on the third dielectric layer made of carbon containing SiO2, the first and second dielectric layers having a via hole, the third dielectric layer having a recess overlapping the via hole, the recess formed to communicate with the via hole, a metal plug formed in the via hole in contact with the lower wiring layer or the electronic elements in the substrate, a metal wiring layer formed in the recess, and a fourth dielectric layer to cover the metal wiring layer.

Abstract: A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A two-stage amplifier of a first-stage amplifier 21 and second-stage amplifiers 22 and 23 is provided. A writing mode and reproducing modes are switched in the first-stage amplifier 21 by switching a parallel circuit of a feedback capacitor Cf1w and a feedback resistor Rf1w and a parallel circuit of a feedback capacitor Cf1r and a feedback resistor Rf1r. The second-stage amplifier 23 is provided with feedback resistors Rf22 and Rf23 that are connected to each other in parallel. The feedback resistor Rf23 is connected in the feedback loop by a switch transistor QSW only when reproducing a high-reflective disk. This enables an amplifier gain to be suitably set for each of writing, low-reflective disk reproducing, and high-reflective disk reproducing. As a result, desirable reproducing characteristics can be obtained for the low-reflective disk while accommodating high-speed writing with a large laser power.

Abstract: It is an object of the present invention to provide, in the double wire type welding method, a consumable electrode type arc welding method and welding apparatus for which the welding speed is sufficiently increased, and in particular the melting of steel such as carbon steel is increased and hence the welding speed is increased.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A hot water type first idle control device includes a heating chamber through which cooling water for an engine is allowed to flow, a wax case heated by the heating chamber, and a device housing in which the wax case is accommodated and retained. In the hot water type first idle control device, the heating chamber is integrally defined in the device housing to adjoin the wax case with a partition wall interposed therebetween for separating the heating chamber from the inside of the device housing. Thus, it is possible to effectively heat the wax case by hot water, while preventing the entering of the hot water into the device housing.

Abstract: A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.

Abstract: An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—E bond or a Si—CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.