Patents by Inventor Takashi Yokoyama
Takashi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050224847Abstract: The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.Type: ApplicationFiled: March 16, 2005Publication date: October 13, 2005Applicants: Fujio Masuoka, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Shinji Horii, Takuji Tanigami, Takashi Yokoyama
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Patent number: 6933556Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.Type: GrantFiled: June 20, 2002Date of Patent: August 23, 2005Assignees: Sharp Kabushiki KaishaInventors: Tetsuo Endoh, Fujio Masuoka, Takuji Tanigami, Takashi Yokoyama, Noboru Takeuchi
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Publication number: 20050169043Abstract: A semiconductor memory device comprises a memory array on a semiconductor substrate having a constitution such that a plurality of memory cells where one end of the variable resistive element is connected to either an emitter or a collector of a bipolar transistor are arranged in the row and the column directions in a matrix form, the other of the emitter or the collector of the bipolar transistor in each memory cell in the same column is connected to common source line extending in the column direction, a base of the bipolar transistor in each memory cell in the same row is connected to common word line extending in the row direction, the other end of the variable resistive element in each memory cell in the same column is connected to common bit line extending in the column direction.Type: ApplicationFiled: January 27, 2005Publication date: August 4, 2005Inventors: Takashi Yokoyama, Takuji Tanigami
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Publication number: 20050157722Abstract: A server having a function of authenticating a user, a function of confirming a connection state of the user by periodically transmitting a re-authentication request packet or a connection confirmation packet to the user and receiving a response, and a function of setting policy routing of an access server is used. A terminal communicates with the server instead of a Web browser to perform authentication at the initial start-up stage, and activates a client for responding to the re-authentication request packet or connection confirmation packet to thereby retain the connection state. Alternatively, a server having a function of authenticating a user is installed at the position of the authentication Web server. The terminal communicates with the server instead of the Web browser to perform authentication at the initial start-up stage, and a client for periodically performing authentication is activated thereafter to thereby retain the connection state.Type: ApplicationFiled: July 20, 2004Publication date: July 21, 2005Inventors: Tetsuro Yoshimoto, Masatoshi Takihiro, Takashi Yokoyama
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Patent number: 6919622Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: February 10, 2004Date of Patent: July 19, 2005Assignee: Renesas Technology Corp.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Publication number: 20050124168Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).Type: ApplicationFiled: October 21, 2004Publication date: June 9, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
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Publication number: 20050101087Abstract: The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.Type: ApplicationFiled: December 4, 2003Publication date: May 12, 2005Applicant: SHARP KABUSHIKI KAISHAInventors: Tetsuo Endoh, Fujio Masuoka, Takuji Tanigami, Takashi Yokoyama, Shinji Horii
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Patent number: 6870215Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and memory cells each constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein the memory cells are disposed in series, and the island-like semiconductor layer on which the memory cells are disposed has cross-sectional areas in a horizontal direction which vary stepwise.Type: GrantFiled: June 20, 2002Date of Patent: March 22, 2005Assignees: Sharp Kabushiki KaishaInventors: Tetsuo Endoh, Fujio Masuoka, Takuji Tanigami, Takashi Yokoyama, Noboru Takeuchi, Yoshihisa Wada, Kota Sato, Kazushi Kinoshita
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Patent number: 6863330Abstract: A seat device adapted to be fixed to engagement members on a vehicle floor includes a first engagement member supporting a front portion of the seat device, a second engagement member supporting a rear portion of the seat, a first lock engagable with the first engagement member, a second lock engagable with the second engagement member. The first lock is supported on the seat device and includes a bracket rotatably supported relative to the seat device and being engagable with the first engagement member and a hook member supported on the bracket and being able to maintain an engagement of the bracket with the first engagement member. A contact portion is provided on the hook member for contacting on a portion of the seat device to prevent a release operation of the hook member when the bracket is out of a predetermined position range relative to the seat device.Type: GrantFiled: July 29, 2003Date of Patent: March 8, 2005Assignee: Aisin Seiki Kabushiki KaishaInventors: Takashi Yokoyama, Hiroyuki Okazaki, Yukifumi Yamada
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Publication number: 20050035399Abstract: A semiconductor device comprising a memory cell which includes: a pillar-shaped semiconductor layer of a first conductive type formed on a semiconductor substrate; source and drain diffusion layers of a second conductive type formed in upper and lower portions of the pillar-shaped semiconductor layer; a semiconductor layer of the second conductive type or a cavity formed inside the pillar-shaped semiconductor layer; and a gate electrode formed on a side face of the pillar-shaped semiconductor layer via a gate insulating film, or a control gate electrode formed on the side face of the pillar-shaped semiconductor layer via a charge accumulation layer.Type: ApplicationFiled: August 4, 2004Publication date: February 17, 2005Applicants: Fujio Masuoka, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Shinji Horii, Takuji Tanigami, Takashi Yokoyama, Noboru Takeuchi
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Publication number: 20050037600Abstract: An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plane extending at a predetermined angle with respect to the one direction, thereby controlling a direction of the ion implantation to the side wall.Type: ApplicationFiled: August 12, 2004Publication date: February 17, 2005Applicants: FUJIO MASUOKA, SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Shinji Horii, Takuji Tanigami, Takashi Yokoyama
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Publication number: 20050037621Abstract: An etching method for a semiconductor device comprising the steps of: generating an etching species atmosphere above the semiconductor device having a step composed of a main surface and a sidewall; and applying an electric field to accelerate the etching species in one direction and a magnetic field along a plane that crosses the one direction at a specific angle so that the sidewall is etched.Type: ApplicationFiled: August 11, 2004Publication date: February 17, 2005Applicants: SHARP KABUSHIKI KAISHAInventors: Fujio Masuoka, Shinji Horii, Takuji Tanigami, Takashi Yokoyama
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Publication number: 20050032320Abstract: A method for manufacturing a semiconductor device is provided, which is consisting of the steps of: forming a transistor on a surface region of a semiconductor substrate which is isolated by an insulating isolation region; forming an inter-layer insulation film provide with a hydrogen supplying path that reaches said isolation region on said semiconductor substrate on which said transistor is formed; and supplying hydrogen in said semiconductor substrate from said hydrogen supplying path through said isolation region by carrying out heat treatment. And also the semiconductor device is provided manufactured thereby.Type: ApplicationFiled: August 4, 2004Publication date: February 10, 2005Inventor: Takashi Yokoyama
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Publication number: 20040258023Abstract: A communication system includes a control unit, a switch and a diversity hand-over processing unit connected to the control unit and the switch for receiving both a first communication signal received from a radio base station which outputs the hand-over instruction, and a second communication signal received from another radio base station to which the communication signal will be hand-over so as to output one of the first and second communication signals to the associated interface circuit. The diversity hand-over processing unit transmits the communication signal received through the radio base station from the mobile station on the reception side for communication to both the interface circuit associated with the radio base station as a source of hand-over and the interface circuit associated with the radio base station as a destination of hand-over.Type: ApplicationFiled: July 20, 2004Publication date: December 23, 2004Inventors: Kenichi Sakamoto, Tsutomu Kusaki, Masaru Murakami, Takashi Yokoyama
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Publication number: 20040238879Abstract: The present invention provides a semiconductor memory device comprising one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, whereinType: ApplicationFiled: May 25, 2004Publication date: December 2, 2004Applicants: FUJIO MASUOKA, SHARP KABUSHIKI KAISHAInventors: Tetsuo Endoh, Fujio Masuoka, Shinji Horii, Takuji Tanigami, Yoshihisa Wada, Takashi Yokoyama, Noboru Takeuchi
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Patent number: 6821687Abstract: A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.Type: GrantFiled: April 2, 2002Date of Patent: November 23, 2004Assignee: NEC Electronics CorporationInventors: Nobuaki Hamanaka, Takashi Yokoyama, Kazutoshi Shiba, Noriaki Oda
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Publication number: 20040213279Abstract: In a mobile communication system having an ATM-processed transfer path, a non-instantaneous interrupt handover can be realized. In a mobile communication network including an ATM-processed transfer path, when a mobile station is moved between cells during communication, frames are received to be identified by a mobile switching center. The frames contain the same data received from both base stations covering the cell range at asynchronous timing different from each other. A selection is made of header information with the lowest error rate from the header information of these frames. The frames are connected at instructed timing. Also, the frames to be transmitted to a plurality of base stations are duplicated, and then transmission timing is specified from these header information. These duplicated frames are transmitted at the specified transmission timing, so that the non-instantaneous interrupt handover is carried out.Type: ApplicationFiled: May 13, 2004Publication date: October 28, 2004Inventors: Tsutomu Kusaki, Kenichi Sakamoto, Masaru Murakami, Takashi Yokoyama
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Publication number: 20040202125Abstract: A communication system includes a control unit, a switch and a diversity hand-over processing unit connected to the control unit and the switch for receiving, both a first communication signal received from a radio base station which outputs the hand-over instruction, and a second communication signal which receives it from another radio base station to which the communication signal will be hand-over to output one of the first and second communication signals to the associated interface circuit, and for transmitting the communication signal received through the radio base station from the mobile station on the reception side for communication to both the interface circuit associated with the radio base station as a source of hand-over and the interface circuit associated with the radio base station as a destination of hand-over.Type: ApplicationFiled: July 18, 2001Publication date: October 14, 2004Inventors: Kenichi Sakamoto, Tsutomu Kusaki, Masaru Murakami, Takashi Yokoyama
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Publication number: 20040183327Abstract: A vehicle seat apparatus includes a first latch mechanism supported at a front portion of a seat cushion frame supporting a vehicle seat, a second latch mechanism supported at a rear portion of the seat cushion frame, a first striker mechanism provided on a vehicle floor and being engagable and disengagable relative to the first latch mechanism, a second striker mechanism provided on the vehicle floor and being engagable and disengagable relative to the second latch mechanism, an upper bracket provided at the first latch mechanism and fixed to the seat cushion frame, and a lower bracket provided at the first latch mechanism and rotatably supported at the upper bracket by a rotating shaft. The upper bracket includes a supporting portion, and the lower bracket moves to be disengaged from the first striker mechanism due to a contact of the supporting portion to the vehicle floor side while the vehicle seat being tumbled is reclined in the rear direction of the vehicle.Type: ApplicationFiled: December 23, 2003Publication date: September 23, 2004Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Takashi Yokoyama, Takahiro Ishijima
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Patent number: 6795414Abstract: A communication system includes a control unit, a switch and a diversity hand-over processing unit connected to the control unit and the switch for receiving both a first communication signal received from a radio base station which outputs the hand-over instruction, and a second communication signal received from another radio base station to which the communication signal will be hand-over so as to output one of the first and second communication signals to the associated interface circuit. The diversity hand-over processing unit transmits the communication signal received through the radio base station from the mobile station on the reception side for communication to both the interface circuit associated with the radio base station as a source of hand-over and the interface circuit associated with the radio base station as a destination of hand-over.Type: GrantFiled: July 18, 2001Date of Patent: September 21, 2004Assignee: Hitachi, Ltd.Inventors: Kenichi Sakamoto, Tsutomu Kusaki, Masaru Murakami, Takashi Yokoyama