Abstract: A vehicle seat is provided with a seat cushion and a seat back. The seat back is provided with a resin frame at least a part of the rear surface side of which is exposed; a pad material disposed on the resin frame; a trim cover for covering the pad material; and a resin hook mounted to an end of the trim cover. The resin frame has a turned-back end formed by turning back outward in a U shape an end of the resin frame. The resin hook is engaged with the turned-back end. The resin hook has a protrusion at the portion thereof which is located within the turned-back end.

Abstract: A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

Abstract: A treatment apparatus and a sterilization apparatus each include a liquid reservoir portion configured to store a treatment subject liquid, a plasma generation portion configured to generate a plasma on or above a liquid surface of the treatment subject liquid, and a bubble supply portion configured to generate a bubble containing the generated plasma on or above the liquid surface and configured to supply the bubble into the treatment subject liquid. Thus, the plasma is generated on or above the liquid surface of the treatment subject liquid, and the bubble containing the generated plasma is generated and supplied into the treatment subject liquid.

Abstract: A semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.

Abstract: A gas turbine blade having a film cooling structure can reduce stress and strain that occur around the cooling holes of the film cooling structure. For example, in the gas turbine blade, a plurality of cooling holes thoroughly connected to the cooling pass formed inside the gas turbine blade are arranged in the span direction in the leading edge portion of the gas turbine blade, and the direction of the longitudinal axis of the cooling holes is made identical to the direction of principal strain occurring in the leading edge portion of the turbine blade within a range of 15 degrees.

Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

Abstract: There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.

Abstract: A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).

Abstract: A semiconductor device including a semiconductor substrate with a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.

Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

Abstract: There is provided a silicon single crystal producing method in producing a silicon single crystal by the Czochralski method using a pulling apparatus including a heat shield, wherein an oxygen concentration in the crystal is controlled through the adjustment of a flow velocity of inert gas introduced into the apparatus at the gap portion between an exterior surface of the single crystal and a lower-end opening edge of the heat shield, in accordance with a gap-to-crystal-diameter ratio (“the area of the gap portion”/“the area of a cross-sectional of the single crystal”). By this producing method, it is possible to appropriately control the oxygen concentration in the pulled single crystal.

Abstract: A semiconductor device includes: a semiconductor substrate including a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.

Abstract: Upon receipt of an intercepted first Ethernet Frame, a communication system converts the first Ethernet Frame into a second Ethernet Frame including a second identifier based on the first identifier and the conversion information, and sends the second Ethernet Frame toward a first input/output port identified by the second identifier. The system, in sending an Ethernet Frame on which communication service has been executed from the virtual machine, converts the Ethernet Frame on which the communication service has been executed into a third Ethernet Frame including a third identifier identifying a second input/output port of the virtual machine which has executed the communication service. The system converts the third Ethernet Frame into the first Ethernet Frame including the first identifier based on the third identifier and the conversion information and sends the first Ethernet Frame toward the destination of the first Ethernet Frame.

Abstract: A graphite spheroidizing agent containing: 30-80 wt % of Si; Mg; RE (rare earth element) which comprises Ce with a purity level of 80-100 wt % or La with a purity level of 80-100 wt %; Ca; and Al is used. The graphite spheroidizing agent is added so as to satisfy the conditions that an amount of RE equivalent to 0.001-0.009 wt % of the total weight of the molten metal, an amount of Ca equivalent to 0.001-0.02 wt % of the total weight of the molten metal, and an amount of Al equivalent to 0.001-0.02 wt % of the total weight of the molten metal are added to the molten metal, and that the molten metal contains 0.03-0.07 wt % of Mg after the graphite spheroidizing treatment. It is possible to suppress crystallization of chunky graphite in a thick section of spheroidal graphite cast iron and deterioration of mechanical properties, with a low cost.

Abstract: A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other.

Abstract: A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Abstract: A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other.

Abstract: A semiconductor device includes: a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Abstract: There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.