Patents by Inventor Takashi Yokoyama

Takashi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7263046
    Abstract: A two-stage amplifier of a first-stage amplifier 21 and second-stage amplifiers 22 and 23 is provided. A writing mode and reproducing modes are switched in the first-stage amplifier 21 by switching a parallel circuit of a feedback capacitor Cf1w and a feedback resistor Rf1w and a parallel circuit of a feedback capacitor Cf1r and a feedback resistor Rf1r. The second-stage amplifier 23 is provided with feedback resistors Rf22 and Rf23 that are connected to each other in parallel. The feedback resistor Rf23 is connected in the feedback loop by a switch transistor QSW only when reproducing a high-reflective disk. This enables an amplifier gain to be suitably set for each of writing, low-reflective disk reproducing, and high-reflective disk reproducing. As a result, desirable reproducing characteristics can be obtained for the low-reflective disk while accommodating high-speed writing with a large laser power.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: August 28, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takanori Okuda, Takashi Yokoyama
  • Publication number: 20070175394
    Abstract: A film forming apparatus is provided that can prevent source gases from reacting together before reaching the substrate being processed in the apparatus, minimize the influence of the radiation heat from the substrate, and make the gas behavior in the reaction chamber better for crystal film formation. The apparatus forms a film on a surface of a heated substrate 5 by causing a first source gas and a second source gas to react together. The apparatus has a processing chamber 1, in which the substrate 5 is placed. The processing chamber 1 is divided into a heating chamber 1a and a reaction chamber 1b by at least the substrate 5 so that the substrate surface can be exposed to the source gases in the reaction chamber 1b. The apparatus further has an exhaust duct 7, through which the exhaust gas can be discharged. The exhaust duct 7 faces the exposed substrate surface and connects with the reaction chamber 1b.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 2, 2007
    Inventors: Toru Inagaki, Takahiro Shirahata, Takashi Yokoyama, Michihiro Sano, Naochika Horio
  • Publication number: 20070172649
    Abstract: An adhesive material and a pressure sensitive adhesive film containing the same of the present invention are characterized in that they satisfy the following requirements (a) and (b). These adhesive material and pressure sensitive adhesive film of the present invention exhibit excellent stability against not only light and heat but also various chemicals. Consequently, they are suitable applications in surface protection uses, transport storage uses, heating treatment uses, grinding/polishing uses, cutting processing uses and transport/storage uses in the fields of electronic/semiconductor materials, optical/display materials and the like, where demands for performances and qualities are strict. The above requirements are: (a) an olefinic polymer is contained, and (b) by measurement according to a differential scanning calorimetry test, the melting temperature Tm is in the range of 80° C. to 180° C. and the heat of fusion ?H is at least 1 J/g.
    Type: Application
    Filed: March 18, 2005
    Publication date: July 26, 2007
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Shin Aihara, Katsutoshi Ozaki, Ryoji Mori, Masumi Saruwatari, Takashi Yokoyama
  • Publication number: 20070165633
    Abstract: When multicast distribution is performed on a network where a point-to-point connection is made between user terminals and a multicast router, the multicast router is protected from load due to response reports, join requests, or leave statements sent from the user terminals simultaneously. If the user terminals send response reports simultaneously, a Layer 2 switch disposed between the user terminals and the multicast router limits response reports sent to the multicast router. The Layer 2 switch prevents response reports sent from the same user terminal from being discarded consecutively, by sending a response report sent from the same user terminal to the multicast router 200 with priority in the next join confirmation event. If the user terminals send join requests or leave statements simultaneously, the Layer 2 switch limits the join requests or leave statements sent to the multicast router 200 in the same manner.
    Type: Application
    Filed: August 23, 2006
    Publication date: July 19, 2007
    Inventors: Kozo Ikegami, Takashi Yokoyama, Minoru Nagai, Yoshitaka Sakamoto, Shigehiro Onizawa
  • Patent number: 7217654
    Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: May 15, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
  • Patent number: 7213861
    Abstract: A retractable seat device includes a seat body having first and second ends rotatably connected to rear and front legs, respectively, first and second arms, and a link. When the first arm is rotated in a second direction, the rear leg and the front leg connected to the rear leg with the link are unfolded, a rear lock mechanism provided on the rear leg becomes engaged with a first striker provided on the vehicle floor, and then a front lock mechanism provided on the front leg becomes engaged with a second striker provided on the vehicle floor, so that the seat body is supported on the vehicle floor by the rear leg and the front leg. The rear lock mechanism has an interlock structure including a ratchet and a pawl, and the front lock mechanism has a hook lock structure including a hook.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 8, 2007
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Takashi Yokoyama, Naoaki Hoshihara
  • Publication number: 20070096331
    Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.
    Type: Application
    Filed: December 18, 2006
    Publication date: May 3, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
  • Publication number: 20070019517
    Abstract: A two-stage amplifier of a first-stage amplifier 21 and second-stage amplifiers 22 and 23 is provided. A writing mode and reproducing modes are switched in the first-stage amplifier 21 by switching a parallel circuit of a feedback capacitor Cf1w and a feedback resistor Rf1w and a parallel circuit of a feedback capacitor Cf1r and a feedback resistor Rf1r. The second-stage amplifier 23 is provided with feedback resistors Rf22 and Rf23 that are connected to each other in parallel. The feedback resistor Rf23 is connected in the feedback loop by a switch transistor QSW only when reproducing a high-reflective disk. This enables an amplifier gain to be suitably set for each of writing, low-reflective disk reproducing, and high-reflective disk reproducing. As a result, desirable reproducing characteristics can be obtained for the low-reflective disk while accommodating high-speed writing with a large laser power.
    Type: Application
    Filed: September 19, 2006
    Publication date: January 25, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takanori Okuda, Takashi Yokoyama
  • Publication number: 20060289942
    Abstract: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.
    Type: Application
    Filed: June 26, 2006
    Publication date: December 28, 2006
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Horii, Takashi Yokoyama, Tetsuya Ohnishi
  • Publication number: 20060266569
    Abstract: A controller for an electric four-wheel-drive vehicle, which can ensure smooth running performance of the vehicle, an electric driving system, and an electric four-wheel-drive vehicle using the controller. A first wheel is driven by an engine, a second wheel is driven by a motor, and a driving force of the engine is transmitted to the first wheel through a manual transmission and a clutch. When the clutch is in a partially engaged state, a controller (4WDCU) receives an input signal representing a degree of engagement of and clutch and outputs a signal to control a driving force of the motor in accordance with the input signal. When the vehicle starts running and no slips occurs in the wheels, the 4WDCU outputs the signal to gradually increase the driving force of the motor as the engagement of the clutch is progressed.
    Type: Application
    Filed: May 30, 2006
    Publication date: November 30, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Shin Fujiwara, Norikazu Matsuzaki, Takashi Yokoyama
  • Patent number: 7141506
    Abstract: A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: November 28, 2006
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Endoh, Fujio Masuoka, Noboru Takeuchi, Takuji Tanigami, Takashi Yokoyama
  • Patent number: 7135726
    Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: November 14, 2006
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Endoh, Fujio Masuoka, Takuji Tanigami, Takashi Yokoyama, Noboru Takeuchi
  • Patent number: 7133346
    Abstract: A two-stage amplifier of a first-stage amplifier 21 and second-stage amplifiers 22 and 23 is provided. A writing mode and reproducing modes are switched in the first-stage amplifier 21 by switching a parallel circuit of a feedback capacitor Cf1w and a feedback resistor Rf1w and a parallel circuit of a feedback capacitor Cf1r and a feedback resistor Rf1r. The second-stage amplifier 23 is provided with feedback resistors Rf22 and Rf23 that are connected to each other in parallel. The feedback resistor Rf23 is connected in the feedback loop by a switch transistor QSW only when reproducing a high-reflective disk. This enables an amplifier gain to be suitably set for each of writing, low-reflective disk reproducing, and high-reflective disk reproducing. As a result, desirable reproducing characteristics can be obtained for the low-reflective disk while accommodating high-speed writing with a large laser power.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: November 7, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takanori Okuda, Takashi Yokoyama
  • Patent number: 7079513
    Abstract: A communication system includes a control unit, a switch and a diversity hand-over processing unit connected to the control unit and the switch for receiving both a first communication signal received from a radio base station which outputs the hand-over instruction, and a second communication signal received from another radio base station to which the communication signal will be hand-over so as to output one of the first and second communication signals to the associated interface circuit. The diversity hand-over processing unit transmits the communication signal received through the radio base station from the mobile station on the reception side for communication to both the interface circuit associated with the radio base station as a source of hand-over and the interface circuit associated with the radio base station as a destination of hand-over.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: July 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Sakamoto, Tsutomu Kusaki, Masaru Murakami, Takashi Yokoyama
  • Patent number: 7061038
    Abstract: The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: June 13, 2006
    Assignees: Sharp Kabushiki Kaisha, Fujio Masuoka
    Inventors: Tetsuo Endoh, Fujio Masuoka, Takuji Tanigami, Takashi Yokoyama, Shinji Horii
  • Patent number: 7060598
    Abstract: An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plane extending at a predetermined angle with respect to the one direction, thereby controlling a direction of the ion implantation to the side wall.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: June 13, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Fujio Masuoka, Shinji Horii, Takuji Tanigami, Takashi Yokoyama
  • Publication number: 20060016387
    Abstract: The production yield about defect free devices is improved by so controlling the size and density of void defects that they are under predetermined levels without marring the productivity. The pull-up speed V of a silicon crystal (10) by a pull-up mechanism (4) is controlled, and the rate of cooling by a cooler (30) is also controlled. As a result, the axial temperature gradient G1 at and near the melting point of the silicon crystal (10) is increased. The growth condition V/G1 is lowered to a temperature near the critical value under the condition that the growth rate V lies in the range from 97% to 75% of the limit rate Vmax and that the solid-liquid interface is convex with respect to the melt surface. Thus a silicon crystal (10) is grown by pulling up.
    Type: Application
    Filed: November 14, 2003
    Publication date: January 26, 2006
    Inventors: Takashi Yokoyama, Koji Yoshihara, Toshiaki Saishoji, Kozo Nakamura, Ryota Suewa
  • Publication number: 20050285424
    Abstract: A retractable seat device includes a seat body having first and second ends rotatably connected to rear and front legs, respectively, first and second arms, and a link. When the first arm is rotated in a second direction, the rear leg and the front leg connected to the rear leg with the link are unfolded, a rear lock mechanism provided on the rear leg becomes engaged with a first striker provided on the vehicle floor, and then a front lock mechanism provided on the front leg becomes engaged with a second striker provided on the vehicle floor, so that the seat body is supported on the vehicle floor by the rear leg and the front leg. The rear lock mechanism has an interlock structure including a ratchet and a pawl, and the front lock mechanism has a hook lock structure including a hook.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 29, 2005
    Inventors: Takashi Yokoyama, Naoaki Hoshihara
  • Patent number: 6974173
    Abstract: A vehicle seat apparatus includes a first latch mechanism supported at a front portion of a seat cushion frame supporting a vehicle seat, a second latch mechanism supported at a rear portion of the seat cushion frame, a first striker mechanism provided on a vehicle floor and being engagable and disengagable relative to the first latch mechanism, a second striker mechanism provided on the vehicle floor and being engagable and disengagable relative to the second latch mechanism, an upper bracket provided at the first latch mechanism and fixed to the seat cushion frame, and a lower bracket provided at the first latch mechanism and rotatably supported at the upper bracket by a rotating shaft. The upper bracket includes a supporting portion, and the lower bracket moves to be disengaged from the first striker mechanism due to a contact of the supporting portion to the vehicle floor side while the vehicle seat being tumbled is reclined in the rear direction of the vehicle.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: December 13, 2005
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Takashi Yokoyama, Takahiro Ishijima
  • Publication number: 20050224847
    Abstract: The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.
    Type: Application
    Filed: March 16, 2005
    Publication date: October 13, 2005
    Applicants: Fujio Masuoka, SHARP KABUSHIKI KAISHA
    Inventors: Fujio Masuoka, Shinji Horii, Takuji Tanigami, Takashi Yokoyama