Patents by Inventor Takeshi Aoki

Takeshi Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9564399
    Abstract: A method of manufacturing a solid state image sensor is provided. The method includes forming electrically conductive layer and an interlayer insulation film above a first region and a second region, performing an annealing process after forming the conductive layer and the interlayer insulation film, and forming a protective film above the interlayer insulation film and the electrically conductive layer. The electrically conductive layer includes a light shielding layer arranged above the second region. The interlayer insulation film includes a first portion located above the first region and a second portion located above the second region and below the light shielding layer. Before performing the annealing process, an average hydrogen concentration of the second portion is higher than an average hydrogen concentration of the first portion.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: February 7, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takeshi Aoki
  • Publication number: 20160380630
    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 29, 2016
    Inventors: Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA, Takeshi AOKI
  • Patent number: 9515107
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: December 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Publication number: 20160353044
    Abstract: A photoelectric conversion device has an insulator film disposed on a silicon layer having a photoelectric conversion region, the insulator film having a portion overlapped with the photoelectric conversion region, a silicon oxide film disposed on the insulator film, the silicon oxide film having a portion overlapped with the photoelectric conversion region, an electroconductive member disposed between the insulator film and the silicon oxide film, and a silicon oxide layer disposed between the electroconductive member and the silicon oxide film, in which the portion overlapped with the photoelectric conversion region of the silicon oxide film is in contact with the portion overlapped with the photoelectric conversion region of the insulator film and the hydrogen concentration of the silicon oxide film is greater than the hydrogen concentration of the silicon oxide layer.
    Type: Application
    Filed: May 26, 2016
    Publication date: December 1, 2016
    Inventors: Akihiro Kawano, Yukinobu Suzuki, Nobutaka Ukigaya, Takayasu Kanesada, Takeshi Aoki, Hiroshi Takakusagi
  • Publication number: 20160329374
    Abstract: A method of manufacturing a photoelectric conversion device includes forming, with material containing aluminum, an electrically conductive pattern on a semiconductor substrate including a photoelectric converter, forming, on the electrically conductive pattern, an insulating film containing hydrogen, performing first annealing in a hydrogen-containing atmosphere, forming, on the insulating film, a protective film having lower hydrogen permeability than that of the insulating film after the first annealing, and performing second annealing in the hydrogen-containing atmosphere. Temperature in the first annealing is not less than temperature when forming the insulating film and not more than temperature when forming the protective film.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 10, 2016
    Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yukinobu Suzuki
  • Patent number: 9483978
    Abstract: A display device includes a display unit having display elements arrayed in rows and columns. The display elements each include a current-driven light emitting unit and a drive circuit for driving the light emitting unit. A power supply unit supplies a drive voltage for driving the display elements to power supply lines corresponding to the rows of display elements. A signal output unit supplies video signal voltages to data lines corresponding to the columns of the display elements. A control unit detects maximum grayscale values of input signals corresponding to the display elements arranged in the rows, and accordingly controls duty ratios of the drive voltage supplied to the power supply lines corresponding to the rows of the display elements. The control unit also controls values of video signals corresponding to the display elements in each row.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: November 1, 2016
    Assignee: JOLED Inc.
    Inventor: Takeshi Aoki
  • Publication number: 20160311202
    Abstract: A laminated foam interleaf sheet for being interposed between glass plates, having a foam layer of a polyethylene-based resin, and an antistatic layer which is laminated on each of both sides of the foam layer and contains a polyethylene-based resin, a polystyrene-based resin and a polymeric antistatic agent, the laminated foam interleaf sheet having a surface roughness Ra of 30 ?m or less.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 27, 2016
    Applicant: JSP CORPORATION
    Inventors: Takeshi AOKI, Takashi NISHIMOTO, Ryohei TAKEUCHI
  • Patent number: 9473714
    Abstract: An object is to provide a solid-state imaging device or a semiconductor display device with which a high-quality image can be taken. By performing operation using a global shutter method, a potential for controlling charge accumulation operation can be shared by all pixels. In addition, a first photosensor group includes a plurality of photosensors connected to a wiring supplied with an output signal, and a second photosensor group includes a plurality of photosensors connected to another wiring supplied with the output signal. A wiring for supplying a potential or a signal for controlling charge accumulation operation to the first photosensor group is connected to a wiring for supplying the potential or signal to the second photosensor group.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: October 18, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takeshi Aoki, Hikaru Tamura, Takayuki Ikeda, Yoshiyuki Kurokawa
  • Publication number: 20160293649
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: June 9, 2016
    Publication date: October 6, 2016
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Patent number: 9461646
    Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: October 4, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Yoshiyuki Kurokawa, Takeshi Aoki, Yuki Okamoto
  • Publication number: 20160261272
    Abstract: A novel electronic device including a reconfigurable circuit is provided. In the electronic device including a reconfigurable circuit capable of executing multi-context operation, a context selection signal is locally generated. For example, a context selection signal is generated in the reconfigurable circuit with the use of context determination data contained in an output of another logic block, for example. The range of application of the context selection signal can be set as appropriate by a user. Thus, multi-context operation performed locally and partly enables efficient use of the circuit. Memory usage can be reduced and its efficiency can be improved compared to the case of using global multi-context driving. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: February 23, 2016
    Publication date: September 8, 2016
    Inventors: Takayuki IKEDA, Munehiro KOZUMA, Takeshi AOKI
  • Publication number: 20160226490
    Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.
    Type: Application
    Filed: January 27, 2016
    Publication date: August 4, 2016
    Inventors: Munehiro KOZUMA, Takayuki IKEDA, Yoshiyuki KUROKAWA, Takeshi AOKI, Yuki OKAMOTO
  • Patent number: 9401364
    Abstract: A semiconductor device has a function of storing data and includes an output terminal, a first terminal, a second terminal, a first circuit, and second circuits. The first circuit has a function of keeping the potential of the output terminal to be a high-level or low-level potential. The second circuits each include a first pass transistor and a second pass transistor which are electrically connected in series, a first memory circuit, and a second memory circuit. The first and second memory circuits each have a function of making a potential retention node in an electrically floating state. The potential retention nodes of the first and second memory circuits are electrically connected to gates of the first and second pass transistors, respectively. A transistor including an oxide semiconductor layer may be provided in the first and second memory circuits.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Yoshiyuki Kurokawa, Takeshi Aoki
  • Publication number: 20160204068
    Abstract: A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas.
    Type: Application
    Filed: December 14, 2015
    Publication date: July 14, 2016
    Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yasuhiro Kawabata, Junya Tamaki, Norihiko Nakata, Satoshi Ogawa
  • Patent number: 9384813
    Abstract: A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: July 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Munehiro Kozuma
  • Patent number: 9379711
    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 28, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Takeshi Aoki
  • Patent number: 9348165
    Abstract: It is an object to provide a display device exhibiting high visibility and having a touch recognition function. The display device includes a display portion and a sensor portion. The display portion includes a first liquid crystal element including a polymer-scattered liquid crystal. The sensor portion includes a light-receiving element and a second liquid crystal element including a polymer-dispersed liquid crystal provided over the light-receiving element. The first liquid crystal element and the second liquid crystal element are driven independently from each other. The light-receiving element receives light transmitting through the second liquid crystal element.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: May 24, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Takeshi Aoki
  • Publication number: 20160126270
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: January 8, 2016
    Publication date: May 5, 2016
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Publication number: 20160118426
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: December 31, 2015
    Publication date: April 28, 2016
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Patent number: D767134
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: September 20, 2016
    Assignee: AMMTEC INC.
    Inventors: Takeshi Aoki, Etsuko Ayaka, Shunji Ono