Patents by Inventor Takeshi Aoki

Takeshi Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170316742
    Abstract: Provided is a data driver (102) configured to be used for driving a display unit that includes pixels arranged in a two-dimensional matrix, the data driver including: a resistance circuit (102E) to which a plurality of reference voltages with different values are applied, the resistance circuit including a plurality of output nodes configured to output the reference voltages and voltages obtained by dividing the reference voltages; a selector unit (102G) configured to select one of the plurality of output nodes in accordance with a value of an input gradation signal, and cause a voltage corresponding to the value of the gradation signal to be output; and a phase difference control unit (102C) configured to perform control to delay an output node selection operation by the selector unit (102G) in the case where an input gradation signal is included in a predetermined high tonal range or a predetermined low tonal range.
    Type: Application
    Filed: September 3, 2015
    Publication date: November 2, 2017
    Inventor: TAKESHI AOKI
  • Publication number: 20170294470
    Abstract: Provided are a solid-state image pickup apparatus which includes: a semiconductor substrate having a plurality of photoelectric converters; a first and a second insulating layers formed on the semiconductor substrate; an optical waveguide formed above each of the plurality of photoelectric converters and in an opening portion of the first and the second insulating layers, and has a refractive index higher than a refractive index of the first insulating layer; and a light reflecting layer formed at a boundary between the optical waveguide and the second insulating layer, and has a refractive index lower than a refractive index of the optical waveguide, where the following expression is satisfied: ?<90°, where a represents an angle formed by a boundary surface between the light reflecting layer and the second insulating layer with respect to a boundary surface between the first insulating layer and the second insulating layer.
    Type: Application
    Filed: March 23, 2017
    Publication date: October 12, 2017
    Inventors: Koki Takami, Takeshi Aoki, Yusuke Onuki
  • Patent number: 9761281
    Abstract: To provide a semiconductor device having a novel configuration, in which a malfunction and power consumption are reduced. A data holding circuit which includes a flipflop including first and second latch circuits and a shadow register including a nonvolatile memory portion; and a control signal generation circuit which generates a first control signal supplied to the first latch circuit and a second control signal supplied to the second latch circuit are included. The shadow register is a circuit which controls data saving or data restoring between the first and second latch circuits on the basis of a saving control signal or a restore control signal. The control signal generation circuit is a circuit which generates the first and second control signals at L level in a period during which data is saved or restored, on the basis of a clock signal, the saving control signal, and the restore control signal.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Takayuki Ikeda, Yoshiyuki Kurokawa, Munehiro Kozuma, Takeshi Aoki
  • Patent number: 9755040
    Abstract: To provide a semiconductor wafer having a wafer, a compound semiconductor layer, a first insulating layer and a second insulating layer, wherein in the depth direction, oxygen atoms and nitrogen atoms are continuously distributed, the number of the nitrogen atoms along the depth direction shows its maximum in the first insulating layer, the total number of third atoms and fourth atoms along the depth direction becomes the largest in the compound semiconductor layer, the number of the oxygen atoms at the interface between the compound semiconductor layer and the first insulating layer is smaller than the number of the oxygen atoms at the interface between the first insulating layer and the second insulating layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 5, 2017
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takeshi Aoki, Noboru Fukuhara, Hiroyuki Sazawa
  • Patent number: 9706148
    Abstract: This invention has for purpose to provide a photosensor that is small in size and can obtain high-contrast image data and to provide a semiconductor device including the photosensor. In the photosensor including a light-receiving element, a transistor serving as a switching element, and a charge retention node electrically connected to the light-receiving element through the transistor, the reduction in charge held in the charge retention node is suppressed by extending the fall time of the input waveform of a driving pulse supplied to the transistor to turn off the transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Hikaru Tamura
  • Publication number: 20170194327
    Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Inventor: Takeshi AOKI
  • Patent number: 9673253
    Abstract: A method of manufacturing a photoelectric conversion device includes forming, with material containing aluminum, an electrically conductive pattern on a semiconductor substrate including a photoelectric converter, forming, on the electrically conductive pattern, an insulating film containing hydrogen, performing first annealing in a hydrogen-containing atmosphere, forming, on the insulating film, a protective film having lower hydrogen permeability than that of the insulating film after the first annealing, and performing second annealing in the hydrogen-containing atmosphere. Temperature in the first annealing is not less than temperature when forming the insulating film and not more than temperature when forming the protective film.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 6, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yukinobu Suzuki
  • Patent number: 9640101
    Abstract: There is provided a display apparatus including a display panel where display elements connected to a scanning line and a signal line are arrayed in a two dimensional matrix, and a driving circuit unit configured to drive the display panel, the driving circuit unit including a gate driver configured to feed a scanning signal to the scanning line such that a back gate voltage of a field effect transistor configuring an output buffer for generating the scanning signal is capable of controlling. Also, there is provided an electronic device including the display apparatus.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: May 2, 2017
    Assignee: JOLED Inc.
    Inventors: Takeshi Aoki, Iwao Ushinohama
  • Patent number: 9631060
    Abstract: An extruded foam sheet having a foam layer constituted of a base resin containing low density polyethylene as a major component thereof, wherein the foam sheet has an apparent density of 45 to 450 kg/m3, an average thickness of 0.03 mm or more and less than 0.3 mm and a dimensional change of ?5% to 0% in the extrusion direction when heated at 80° C. for 24 hours and wherein cell walls of the foam layer have an average thickness of 6 to 70 ?m. The foam sheet may be used as an interleaf sheet for glass plates.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: April 25, 2017
    Assignee: JSP CORPORATION
    Inventors: Takashi Nishimoto, Takeshi Aoki
  • Patent number: 9627319
    Abstract: A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 18, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yasuhiro Kawabata, Junya Tamaki, Norihiko Nakata, Satoshi Ogawa
  • Patent number: 9607991
    Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Aoki
  • Publication number: 20170085264
    Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 23, 2017
    Inventors: Munehiro KOZUMA, Takayuki IKEDA, Yoshiyuki KUROKAWA, Takeshi AOKI, Yuki OKAMOTO
  • Publication number: 20170066224
    Abstract: A multi-layer foam sheet with an apparent density of 30 to 300 kg/m3 and a thickness of 0.05 to 2 mm, including a foam layer containing a polyethylene-based resin (A), and an antistatic layer fusion-laminated by coextrusion on each of both sides of the foam layer. The antistatic layer has a basis weight of 1 to 10 g/m2 and contains a polyethylene-based resin (B), a polystyrene-based resin, a styrenic elastomer, and a polymeric antistatic agent, with the polystyrene-based resin being contained in the antistatic layer in an amount of 15 to 70% by weight.
    Type: Application
    Filed: February 26, 2015
    Publication date: March 9, 2017
    Applicant: JSP CORPORATION
    Inventors: Takeshi AOKI, Takashi NISHIMOTO, Mikidai FUJITA, Ryohei TAKEUCHI
  • Patent number: 9589425
    Abstract: Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 7, 2017
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZE GAMING AMERICA, INC.
    Inventors: Yoichi Kato, Hiroaki Kashima, Naoya Shirai, Masumi Fujisawa, Hiroki Nakamura, Takeshi Aoki, Kazuo Okada
  • Publication number: 20170053699
    Abstract: A semiconductor device that has a long data retention time during stop of supply of power supply voltage by reducing leakage current due to miniaturization of a semiconductor element. In a structure where charge corresponding to data is held with the use of low off-state current of a transistor containing an oxide semiconductor in its channel formation region, a transistor for reading data and a transistor for storing charge are separately provided, thereby decreasing leakage current flowing through a gate insulating film.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 23, 2017
    Inventors: Takeshi AOKI, Munehiro KOZUMA, Yoshiyuki KUROKAWA
  • Patent number: 9564399
    Abstract: A method of manufacturing a solid state image sensor is provided. The method includes forming electrically conductive layer and an interlayer insulation film above a first region and a second region, performing an annealing process after forming the conductive layer and the interlayer insulation film, and forming a protective film above the interlayer insulation film and the electrically conductive layer. The electrically conductive layer includes a light shielding layer arranged above the second region. The interlayer insulation film includes a first portion located above the first region and a second portion located above the second region and below the light shielding layer. Before performing the annealing process, an average hydrogen concentration of the second portion is higher than an average hydrogen concentration of the first portion.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: February 7, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takeshi Aoki
  • Publication number: 20160380630
    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 29, 2016
    Inventors: Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA, Takeshi AOKI
  • Patent number: 9515107
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: December 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Publication number: 20160353044
    Abstract: A photoelectric conversion device has an insulator film disposed on a silicon layer having a photoelectric conversion region, the insulator film having a portion overlapped with the photoelectric conversion region, a silicon oxide film disposed on the insulator film, the silicon oxide film having a portion overlapped with the photoelectric conversion region, an electroconductive member disposed between the insulator film and the silicon oxide film, and a silicon oxide layer disposed between the electroconductive member and the silicon oxide film, in which the portion overlapped with the photoelectric conversion region of the silicon oxide film is in contact with the portion overlapped with the photoelectric conversion region of the insulator film and the hydrogen concentration of the silicon oxide film is greater than the hydrogen concentration of the silicon oxide layer.
    Type: Application
    Filed: May 26, 2016
    Publication date: December 1, 2016
    Inventors: Akihiro Kawano, Yukinobu Suzuki, Nobutaka Ukigaya, Takayasu Kanesada, Takeshi Aoki, Hiroshi Takakusagi
  • Publication number: 20160329374
    Abstract: A method of manufacturing a photoelectric conversion device includes forming, with material containing aluminum, an electrically conductive pattern on a semiconductor substrate including a photoelectric converter, forming, on the electrically conductive pattern, an insulating film containing hydrogen, performing first annealing in a hydrogen-containing atmosphere, forming, on the insulating film, a protective film having lower hydrogen permeability than that of the insulating film after the first annealing, and performing second annealing in the hydrogen-containing atmosphere. Temperature in the first annealing is not less than temperature when forming the insulating film and not more than temperature when forming the protective film.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 10, 2016
    Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yukinobu Suzuki