Patents by Inventor Takeshi Aoki

Takeshi Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160104354
    Abstract: Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided.
    Type: Application
    Filed: October 21, 2015
    Publication date: April 14, 2016
    Inventors: Yoichi KATO, Hiroaki KASHIMA, Naoya SHIRAI, Masumi FUJISAWA, Hiroki NAKAMURA, Takeshi AOKI, Kazuo OKADA
  • Publication number: 20160086958
    Abstract: A semiconductor device has a function of storing data and includes an output terminal, a first terminal, a second terminal, a first circuit, and second circuits. The first circuit has a function of keeping the potential of the output terminal to be a high-level or low-level potential. The second circuits each include a first pass transistor and a second pass transistor which are electrically connected in series, a first memory circuit, and a second memory circuit. The first and second memory circuits each have a function of making a potential retention node in an electrically floating state. The potential retention nodes of the first and second memory circuits are electrically connected to gates of the first and second pass transistors, respectively. A transistor including an oxide semiconductor layer may be provided in the first and second memory circuits.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 24, 2016
    Inventors: Munehiro KOZUMA, Takayuki IKEDA, Yoshiyuki KUROKAWA, Takeshi AOKI
  • Publication number: 20160079386
    Abstract: To provide a semiconductor wafer having a wafer, a compound semiconductor layer, a first insulating layer and a second insulating layer, wherein in the depth direction, oxygen atoms and nitrogen atoms are continuously distributed, the number of the nitrogen atoms along the depth direction shows its maximum in the first insulating layer, the total number of third atoms and fourth atoms along the depth direction becomes the largest in the compound semiconductor layer, the number of the oxygen atoms at the interface between the compound semiconductor layer and the first insulating layer is smaller than the number of the oxygen atoms at the interface between the first insulating layer and the second insulating layer.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 17, 2016
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takeshi AOKI, Noboru FUKUHARA, Hiroyuki SAZAWA
  • Patent number: 9283783
    Abstract: A recording apparatus includes a body, an operation panel provided on a front surface of the body, a feeding cassette that accommodates sheets, removably mounted with respect to the body from the front surface of the body, and is configured such that a part thereof is protruded from body in a state of being mounted on the body, a recording section that is disposed inside the body and performs printing by ejecting ink onto a sheet transported from the feeding cassette, a discharging tray that is disposed on the feeding cassette and supports the sheet after printing is completed, and a body-side cover section that is provided in the body and covers both side surfaces of the feeding cassette.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 15, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Yoda, Masanori Nakata, Takeshi Aoki, Toshikazu Kotaka
  • Patent number: 9287878
    Abstract: A dynamic reconfigurable semiconductor device is provided. The semiconductor device includes two logic blocks, a pass transistor, two selection transistors and a precharge transistor. The two selection transistors are arranged to sandwich the pass transistor so that a source and a drain of the pass transistor are located between the sources of the two selection transistors. The sources and the drains of the two selection transistors are located between the two logic blocks. When the two selection transistors are in off-state, a potential can be supplied to the source or the drain of the pass transistor via the precharge transistor, and by electrical conduction, another potential for a context is applied to the gate of the pass transistor. When the context is executed, the gate of the pass transistor is in a floating state, the two selection transistors are in on-state, and the precharge transistor is in off-state.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Nora Bjorklund, Takeshi Aoki, Yoshiyuki Kurokawa
  • Patent number: 9257567
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: February 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Patent number: 9252171
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 2, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Patent number: 9245589
    Abstract: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: January 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 9234473
    Abstract: An air-fuel ratio control apparatus for an internal combustion engine includes an air-fuel ratio detector, a fuel amount controller, an operational state parameter acquiring device, an extractor, a failure determination device, a variation state parameter calculator, and a determination stopping device. The operational state parameter acquiring device is configured to acquire at least one operational state parameter. The failure determination device is configured to execute failure determination of determining a failure in an air-fuel ratio control system of the internal combustion engine based on a specific frequency component extracted by the extractor. The variation state parameter calculator is configured to calculate a variation state parameter. The determination stopping device is configured to stop the failure determination if the variation state parameter calculated by the variation state parameter calculator is equal to or larger than a predetermined threshold value.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 12, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Tooru Sekiguchi, Atsuhiro Miyauchi, Takeshi Aoki, Seiji Watanabe, Kazunori Kawamura, Michinori Tani
  • Publication number: 20160005782
    Abstract: A method of manufacturing a solid state image sensor is provided. The method includes forming electrically conductive layer and an interlayer insulation film above a first region and a second region, performing an annealing process after forming the conductive layer and the interlayer insulation film, and forming a protective film above the interlayer insulation film and the electrically conductive layer. The electrically conductive layer includes a light shielding layer arranged above the second region. The interlayer insulation film includes a first portion located above the first region and a second portion located above the second region and below the light shielding layer. Before performing the annealing process, an average hydrogen concentration of the second portion is higher than an average hydrogen concentration of the first portion.
    Type: Application
    Filed: June 25, 2015
    Publication date: January 7, 2016
    Inventor: Takeshi Aoki
  • Patent number: 9225329
    Abstract: A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 29, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Yoshiyuki Kurokawa, Takeshi Aoki, Takashi Nakagawa
  • Patent number: 9225336
    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: December 29, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Takayuki Ikeda, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Publication number: 20150357476
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Patent number: 9208658
    Abstract: Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 8, 2015
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZE GAMING AMERICA, INC.
    Inventors: Yoichi Kato, Hiroaki Kashima, Naoya Shirai, Masumi Fujisawa, Hiroki Nakamura, Takeshi Aoki, Kazuo Okada
  • Patent number: 9202347
    Abstract: Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 1, 2015
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZE GAMING AMERICA, INC.
    Inventors: Yoichi Kato, Hiroaki Kashima, Naoya Shirai, Masumi Fujisawa, Hiroki Nakamura, Takeshi Aoki, Kazuo Okada
  • Publication number: 20150341035
    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
    Type: Application
    Filed: May 29, 2015
    Publication date: November 26, 2015
    Inventors: Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA, Takeshi AOKI
  • Publication number: 20150311897
    Abstract: A dynamic reconfigurable semiconductor device is provided. The semiconductor device includes two logic blocks, a pass transistor, two selection transistors and a precharge transistor. The two selection transistors are arranged to sandwich the pass transistor so that a source and a drain of the pass transistor are located between the sources of the two selection transistors. The sources and the drains of the two selection transistors are located between the two logic blocks. When the two selection transistors are in off-state, a potential can be supplied to the source or the drain of the pass transistor via the precharge transistor, and by electrical conduction, another potential for a context is applied to the gate of the pass transistor. When the context is executed, the gate of the pass transistor is in a floating state, the two selection transistors are in on-state, and the precharge transistor is in off-state.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 29, 2015
    Inventors: Nora BJORKLUND, Takeshi AOKI, Yoshiyuki KUROKAWA
  • Publication number: 20150302803
    Abstract: A signal output circuit that alternately supplies a reference voltage and a video signal voltage to a data line includes: an output node to which the data line is connected; a reference voltage node to which the reference voltage is applied; a source amplifier that outputs the video signal voltage in accordance with an input gradation signal; a first switch provided between the output side of the source amplifier and the output node; a second switch provided between the reference voltage node and the output node; and a third switch provided in the power supply path of the source amplifier, wherein, during a scanning period for scanning display elements row by row, switching is performed between a state where the first switch is non-conductive while the second switch is conductive and a state where the first switch is conductive while the second switch is non-conductive, and the third switch is put into a conductive state when the first switch is put into a conductive state, and is put into a non-conductive
    Type: Application
    Filed: November 8, 2013
    Publication date: October 22, 2015
    Inventors: Takeshi Aoki, Iwao Ushinohama
  • Patent number: 9156287
    Abstract: A medium transport device includes a medium transport pathway that inverts a medium that is supplied from a processing unit and is capable of transporting the medium to the processing unit again, a plurality of supply units that supply media, and a plurality of convergence units at which the plurality of supply units and the medium transport route converge. A transport roller is provided in each convergence unit.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 13, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Aoki
  • Patent number: 9153619
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki