Patents by Inventor Takeshi Fukunaga

Takeshi Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080224215
    Abstract: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are joined together to form a region having substantially no grain boundaries, i.e., a monodomain region which can substantially be regarded as a single crystal. A semiconductor device is formed by using the monodomain region as an active layer.
    Type: Application
    Filed: May 16, 2008
    Publication date: September 18, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Jun Koyama, Takeshi Fukunaga
  • Patent number: 7414267
    Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: August 19, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroshi Shibata, Takeshi Fukunaga
  • Publication number: 20080116458
    Abstract: An EL display device capable of performing clear multi-gradation color display and electronic equipment provided with the EL display device are provided, wherein gradation display is performed according to a time-division driving method in which the luminescence and non-luminescence of an EL element (109) disposed in a pixel (104) are controlled by time, and the influence by the characteristic variability of a current controlling TFT (108) is prevented. When this method is used, a data signal side driving circuit (102) and a gate signal side driving circuit (103) are formed with TFTs that use a silicon film having a peculiar crystal structure and exhibit an extremely high operation speed.
    Type: Application
    Filed: October 18, 2007
    Publication date: May 22, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio YAMAUCHI, Takeshi FUKUNAGA
  • Patent number: 7375401
    Abstract: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are joined together to form a region having substantially no grain boundaries, i.e., a monodomain region which can substantially be regarded as a single crystal. A semiconductor device is formed by using the monodomain region as an active layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: May 20, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Jun Koyama, Takeshi Fukunaga
  • Patent number: 7372073
    Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and ac active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of silicon film to a crystalline silicon film.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: May 13, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
  • Publication number: 20080102548
    Abstract: In a liquid crystal display device which performs image display by controlling a liquid crystal layer by a lateral electric field that is parallel with a substrate, the lateral electric field is formed by a black matrix and a pixel electrode. That is, a common electrode and a black matrix are commonized which are separately provided conventionally. Further, a storage capacitor is formed in an area where the black matrix and a pixel line coextend with a third interlayer insulating film interposed in between. Since the storage capacitor is formed by using all the area where a thin-film transistor is covered with the black matrix, sufficient capacitance can be secured even if the widths of electrodes and wiring lines are reduced in the future.
    Type: Application
    Filed: December 12, 2007
    Publication date: May 1, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshiharu Hirakata, Takeshi Nishi, Shunpei Yamazaki, Takeshi Fukunaga
  • Patent number: 7339235
    Abstract: A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: March 4, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
  • Publication number: 20080035927
    Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 14, 2008
    Inventors: Shunpei Yamazaki, Yu Yamazaki, Jun Koyama, Takayuki Ikeda, Hiroshi Shibata, Hidehito Kitakado, Takeshi Fukunaga
  • Patent number: 7326604
    Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: February 5, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Toru Mitsuki, Takeshi Fukunaga
  • Publication number: 20080018566
    Abstract: An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.
    Type: Application
    Filed: September 24, 2007
    Publication date: January 24, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yukio YAMAUCHI, Takeshi FUKUNAGA
  • Patent number: 7312572
    Abstract: An EL display device capable of performing clear multi-gradation color display and electronic equipment provided with the EL display device are provided, wherein gradation display is performed according to a time-division driving method in which the luminescence and non-luminescence of an EL element (109) disposed in a pixel (104) are controlled by time, and the influence by the characteristic variability of a current controlling TFT (108) is prevented. When this method is used, a data signal side driving circuit (102) and a gate signal side driving circuit (103) are formed with TFTs that use a silicon film having a peculiar crystal structure and exhibit an extremely high operation speed.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: December 25, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Yamauchi, Takeshi Fukunaga
  • Publication number: 20070291022
    Abstract: In an electrooptical device including an electrooptical modulating layer between a first substrate 101 and a second substrate 105, all edges 107 to 109 of the first substrate 101 and the second substrate 105, except an edge where IC chips 110 and 111 are attached, are trued up each other between the first substrate 101 and the second substrate 105. By this, it is possible to make the area of the first substrate 101 minimum.
    Type: Application
    Filed: August 13, 2007
    Publication date: December 20, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Yoshiharu Hirakata, Takeshi Fukunaga
  • Patent number: 7310121
    Abstract: In a liquid crystal display device which performs image display by controlling a liquid crystal layer by a lateral electric field that is parallel with a substrate, the lateral electric field is formed by a black matrix and a pixel electrode. That is, a common electrode and a black matrix are commonized which are separately provided conventionally. Further, a storage capacitor is formed in an area where the black matrix and a pixel line coextend with a third interlayer insulating film interposed in between. Since the storage capacitor is formed by using all the area where a thin-film transistor is covered with the black matrix, sufficient capacitance can be secured even if the widths of electrodes and wiring lines are reduced in the future.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: December 18, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Takeshi Nishi, Shunpei Yamazaki, Takeshi Fukunaga
  • Patent number: 7301276
    Abstract: A light emitting apparatus with high homogeneity in image quality is provided, which includes anodes 102 on an insulator 101, cathodes 107 orthogonal to the anodes 102, and EL layers 106 interposed between the anodes 102 and the cathodes 107, and auxiliary wirings 103 are electrically connected to the anodes 102. The auxiliary wirings 103 are made of a material lower in resistance than that of the anodes 102, thereby being capable of reducing the wiring resistance of the anodes 102.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: November 27, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Fukunaga
  • Publication number: 20070252206
    Abstract: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of a plurality of crystals which may be columnar crystals and/or capillary crystal substantially parallel to the substrate. The resultant structure is then subject to thermal oxidation in a chosen atmosphere containing halogen, thereby removing away any metallic element as contained in the film. This may enable formation of a mono-domain region in which the individual columnar or capillary crystal is in contact with any adjacent crystals and which is capable of being substantially deemed to be a single-crystalline region without presence or inclusion of any crystal grain boundaries therein. This region is for use in forming the active layer of the transistor.
    Type: Application
    Filed: February 2, 2007
    Publication date: November 1, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
  • Patent number: 7276730
    Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: October 2, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yu Yamazaki, Jun Koyama, Takayuki Ikeda, Hiroshi Shibata, Hidehito Kitakado, Takeshi Fukunaga
  • Patent number: 7274349
    Abstract: An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: September 25, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Yamauchi, Takeshi Fukunaga
  • Patent number: 7268777
    Abstract: There is disclosed an electrooptical device capable of achieving a large area display by making full use of the size of the substrate. An active matrix substrate acts as a driver portion for the reflection-type electrooptical device. A pixel matrix circuit and logic circuitry are formed on the active matrix substrate. At this time, the logic circuitry is disposed, by making use of a dead space in the pixel matrix circuit. The area occupied by the pixel matrix circuit, or image display region, can be enlarged without being limited by the area occupied by the logic circuitry.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: September 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Takeshi Fukunaga
  • Publication number: 20070197118
    Abstract: To provide a bright and highly reliable light-emitting device. An anode (102), an EL layer (103), a cathode (104), and an auxiliary electrode (105) are formed sequentially in lamination on a reflecting electrode (101). Further, the anode (102), the cathode (104), and the auxiliary electrode (105) are either transparent or semi-transparent with respect to visible radiation. In such a structure, lights generated in the EL layer (103) are almost all irradiated to the side of the cathode )104), whereby an effect light emitting area of a pixel is drastically enhanced.
    Type: Application
    Filed: September 1, 2006
    Publication date: August 23, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takeshi Fukunaga, Junya Maruyama
  • Publication number: 20070194362
    Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.
    Type: Application
    Filed: April 23, 2007
    Publication date: August 23, 2007
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroshi Shibata, Takeshi Fukunaga