Patents by Inventor Takeshi Fukunaga
Takeshi Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8339038Abstract: To provide a bright and highly reliable light-emitting device. An anode (102), an EL layer (103), a cathode (104), and an auxiliary electrode (105) are formed sequentially in lamination on a reflecting electrode (101). Further, the anode (102), the cathode (104), and the auxiliary electrode (105) are either transparent or semi-transparent with respect to visible radiation. In such a structure, lights generated in the EL layer (103) are almost all irradiated to the side of the cathode (104), whereby an effect light emitting area of a pixel is drastically enhanced.Type: GrantFiled: January 7, 2011Date of Patent: December 25, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Fukunaga, Junya Maruyama
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Patent number: 8319424Abstract: A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is used to form the PWB side wiring (110), a voltage drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.Type: GrantFiled: October 28, 2011Date of Patent: November 27, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukunaga
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Patent number: 8319224Abstract: To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned along a pixel row to thereby simultaneously apply a red light emitting layer application liquid, a green light emitting layer application liquid, and a blue light emitting layer application liquid in stripe shapes. Heat treatment is then performed to thereby form light emitting layers luminescing each of the colors red, green, and blue.Type: GrantFiled: October 1, 2008Date of Patent: November 27, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kunitaka Yamamoto, Masaaki Hiroki, Takeshi Fukunaga
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Patent number: 8278660Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor having low leak current and high mobility are obtained in the same time in a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.Type: GrantFiled: October 27, 2011Date of Patent: October 2, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Hideki Uochi, Toru Takayama, Takeshi Fukunaga, Yasuhiko Takemura
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Publication number: 20120201955Abstract: A cleaning method of removing a vapor-deposition material adhering to equipments without exposure to the atmosphere is provided. A vapor-deposition material adhering to equipments (components of a film-forming apparatus) such as a substrate holder, a vapor-deposition mask, a mask holder, or an adhesion preventing shield provided in a film-forming chamber are subjected to heat treatment. Because of this, the adhering vapor-deposition material is re-sublimated, and removed by exhaust through a vacuum pump. By including such a cleaning method in the steps of manufacturing an electro-optical device, the manufacturing steps are shortened, and an electro-optical device with high reliability can be realized.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Toru TAKAYAMA, Takeshi FUKUNAGA
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SEMICONDUCTOR DEVICE HAVING A PIXEL MATRIX CIRCUIT THAT INCLUDES A PIXEL TFT AND A STORAGE CAPACITOR
Publication number: 20120199840Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.Type: ApplicationFiled: April 10, 2012Publication date: August 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yu Yamazaki, Jun Koyama, Takayuki Ikeda, Hiroshi Shibata, Hidehito Kitakado, Takeshi Fukunaga -
Patent number: 8222696Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.Type: GrantFiled: April 21, 2009Date of Patent: July 17, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
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Publication number: 20120164801Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.Type: ApplicationFiled: March 5, 2012Publication date: June 28, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Takeshi Fukunaga
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Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
Patent number: 8158980Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.Type: GrantFiled: July 30, 2007Date of Patent: April 17, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yu Yamazaki, Jun Koyama, Takayuki Ikeda, Hiroshi Shibata, Hidehito Kitakado, Takeshi Fukunaga -
Publication number: 20120068266Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor having low leak current and high mobility are obtained in the same time in a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.Type: ApplicationFiled: October 27, 2011Publication date: March 22, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hongyong ZHANG, Hideki Uochi, Toru Takayama, Takeshi Fukunaga, Yasuhiko Takemura
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Patent number: 8139557Abstract: A radio base-station apparatus with improved frame transmission efficiency by avoiding interference of preambles and frame control information between sectors of a cell or between cells with a frequency reuse factor. In the apparatus OFDMA multiple-access processing is performed for each of a plurality of sectors of a cell, and frames made of logical subchannel numbers and OFDMA symbol numbers are configured in synchronization respectively for the plurality of sectors, and offsets are added to the beginnings of given frames such that the preambles and frame control information arranged sequentially from the beginnings of the frames do not overlap on the OFDMA symbol numbers.Type: GrantFiled: September 30, 2005Date of Patent: March 20, 2012Assignee: Mitsubishi Electric CorporationInventors: Tsuyoshi Tominaga, Kunio Satou, Yasuhiro Ohnaka, Takeshi Fukunaga
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Patent number: 8133748Abstract: To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned along a pixel row to thereby simultaneously apply a red light emitting layer application liquid, a green light emitting layer application liquid, and a blue light emitting layer application liquid in stripe shapes. Heat treatment is then performed to thereby form light emitting layers luminescing each of the colors red, green, and blue.Type: GrantFiled: July 10, 2009Date of Patent: March 13, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kunitaka Yamamoto, Masaaki Hiroki, Takeshi Fukunaga
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Publication number: 20120056190Abstract: To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned along a pixel row to thereby simultaneously apply a red light emitting layer application liquid, a green light emitting layer application liquid, and a blue light emitting layer application liquid in stripe shapes. Heat treatment is then performed to thereby form light emitting layers luminescing each of the colors red, green, and blue.Type: ApplicationFiled: September 1, 2011Publication date: March 8, 2012Inventors: Shunpei Yamazaki, Kunitaka Yamamoto, Masaaki Hiroki, Takeshi Fukunaga
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Patent number: 8129232Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.Type: GrantFiled: December 21, 2009Date of Patent: March 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Takeshi Fukunaga
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Publication number: 20120043579Abstract: A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is used to form the PWB side wiring (110), a voltage drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Inventors: Shunpei Yamazaki, Takeshi Fukunaga
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Patent number: 8119189Abstract: An apparatus for forming a film having high uniformity in its film thickness distribution is provided. An evaporation source is used in which an evaporation cell, or a plurality of evaporation cells, having a longitudinal direction is formed, and by moving the evaporation source in a direction perpendicular to the longitudinal direction of the evaporation source, a thin film is deposited on a substrate. By making the evaporation source longer, the uniformity of the film thickness distribution in the longitudinal direction is increased. The evaporation source is moved, film formation is performed over the entire substrate, and therefore the uniformity of the film thickness distribution over the entire substrate can be increased.Type: GrantFiled: December 22, 2000Date of Patent: February 21, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukunaga
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Publication number: 20120034766Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.Type: ApplicationFiled: August 15, 2011Publication date: February 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hisashi OHTANI, Akiharu MIYANAGA, Takeshi FUKUNAGA, Hongyong ZHANG
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Patent number: 8062935Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film an a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.Type: GrantFiled: October 15, 2009Date of Patent: November 22, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Hideki Uochi, Toru Takayama, Takeshi Fukunaga, Yasuhiko Takemura
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Patent number: 8049419Abstract: A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is used to form the PWB side wiring (110), a voltage drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.Type: GrantFiled: April 1, 2009Date of Patent: November 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukunaga
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Publication number: 20110263109Abstract: In an electrooptical device including an electrooptical modulating layer between a first substrate 101 and a second substrate 105, all edges 107 to 109 of the first substrate 101 and the second substrate 105, except an edge where IC chips 110 and 111 are attached, are trued up each other between the first substrate 101 and the second substrate 105. By this, it is possible to make the area of the first substrate 101 minimum.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Yoshiharu HIRAKATA, Takeshi FUKUNAGA