Patents by Inventor Te-An Lin

Te-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME
    Publication number: 20230327006
    Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE
    Publication number: 20230328980
    Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
  • SEMICONDUCTOR BURIED LAYER
    Publication number: 20230326749
    Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Inventors: Hung-Te Lin, Chia-Wei Liu, Hung Chih Yu
  • Method for manufacturing semiconductor device with spacer layer
    Patent number: 11784219
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a dummy gate structure across the fin structure. The method further includes forming a spacer layer on a sidewall of the fin structure at a source/drain region. The method further includes removing at least a portion of the spacer layer to enlarge the source/drain region and forming a source/drain structure in the source/drain region.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mark Van Dal, Gerben Doornbos, Chung-Te Lin
  • Method for forming a semiconductor memory structure using a liner layer as an etch stop
    Patent number: 11785779
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Memory repair using optimized redundancy utilization
    Patent number: 11776647
    Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hao Huang, Cheng-Yi Wu, Katherine H. Chiang, Chung-Te Lin
  • Memory cell with unipolar selectors
    Patent number: 11778836
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a magnetic tunnel junction (MTJ) disposed on a first electrode that is within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector and the second unipolar selector have different widths.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Mauricio Manfrini
  • Semiconductor device with reduced loading effect
    Patent number: 11776850
    Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Lun Chen, Li-Te Lin, Chao-Hsien Huang
  • Memory array staircase structure
    Patent number: 11776602
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Semiconductor structure and method for forming the same
    Patent number: 11777010
    Abstract: A semiconductor structure includes a gate stack over a substrate and a blocking layer disposed between the gate stack and the substrate. The gate stack includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and a first seed layer disposed between the ferroelectric layer and the lower electrode. The blocking layer includes doped hafnium oxide.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • RESIN COMPOSITION AND ARTICLE MADE THEREFROM
    Publication number: 20230303835
    Abstract: A resin composition includes 50 parts by weight of a vinyl-containing polyphenylene ether resin, 1 part by weight to 30 parts by weight of a styrene-butadiene-styrene block copolymer and 0.5 part by weight to 30 parts by weight of a zinc molybdate-covered silica, wherein the zinc molybdate-covered silica has a mass ratio of zinc molybdate to silica of between 1:9 and 2:8. The resin composition may be used to make various articles, such as a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including gel time stability, copper foil peeling strength, difference rate of dissipation factor and conductive anodic filament test.
    Type: Application
    Filed: May 17, 2022
    Publication date: September 28, 2023
    Inventors: Yu-Te LIN, Chien-Cheng WANG
  • 3D ferroelectric memory
    Patent number: 11770935
    Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Carrier barrier layer for tuning a threshold voltage of a ferroelectric memory device
    Patent number: 11769815
    Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Semiconductor device and method for manufacturing the same
    Patent number: 11769822
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, gate spacers, a gate structure. The semiconductor fin is on the substrate. The gate spacers are over the semiconductor fin. The gate structure is on the semiconductor fin and between the gate spacers. The gate structure includes a gate dielectric layer and a first work function metal over the gate dielectric layer, in which a top surface of the first work function metal is lower than a top surface of the gate dielectric layer, and a distance between the top surface of the first work function metal and the top surface of the gate dielectric layer is less than about 1 nm.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao Chang, Li-Te Lin
  • Semiconducting metal oxide transistors having a patterned gate and methods for forming the same
    Patent number: 11757047
    Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • VERTICAL METAL OXIDE SEMICONDUCTOR CHANNEL SELECTOR TRANSISTOR AND METHODS OF FORMING THE SAME
    Publication number: 20230284461
    Abstract: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 7, 2023
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Mauricio Manfrini, Chung-Te Lin, Pin-Cheng Hsu
  • METHOD FOR FINFET FABRICATION AND STRUCTURE THEREOF
    Publication number: 20230282520
    Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.
    Type: Application
    Filed: May 8, 2023
    Publication date: September 7, 2023
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Multinary bit cells for memory devices and network applications and method of manufacturing the same
    Patent number: 11749341
    Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Katherine H. Chiang, Chung-Te Lin
  • SEMICONDUCTOR DEVICE
    Publication number: 20230276712
    Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Hui-Hsien WEI, Wei-Chih WEN, Pin-Ren DAI, Chien-Min LEE, Sheng-Chih LAI, Han-Ting TSAI, Chung-Te LIN
  • Catholic smart rosary
    Patent number: D998278
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 5, 2023
    Assignee: Acer Incorporated
    Inventors: Chun-Te Lin, Tsun-Chih Yang