Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a dummy gate structure across the fin structure. The method further includes forming a spacer layer on a sidewall of the fin structure at a source/drain region. The method further includes removing at least a portion of the spacer layer to enlarge the source/drain region and forming a source/drain structure in the source/drain region.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a magnetic tunnel junction (MTJ) disposed on a first electrode that is within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector and the second unipolar selector have different widths.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: A semiconductor structure includes a gate stack over a substrate and a blocking layer disposed between the gate stack and the substrate. The gate stack includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and a first seed layer disposed between the ferroelectric layer and the lower electrode. The blocking layer includes doped hafnium oxide.

Abstract: A resin composition includes 50 parts by weight of a vinyl-containing polyphenylene ether resin, 1 part by weight to 30 parts by weight of a styrene-butadiene-styrene block copolymer and 0.5 part by weight to 30 parts by weight of a zinc molybdate-covered silica, wherein the zinc molybdate-covered silica has a mass ratio of zinc molybdate to silica of between 1:9 and 2:8. The resin composition may be used to make various articles, such as a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including gel time stability, copper foil peeling strength, difference rate of dissipation factor and conductive anodic filament test.

Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.