Patents by Inventor Thomas Andre

Thomas Andre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid read scheme for spin torque MRAM
    Patent number: 9299411
    Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: March 29, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Chitra Subramanian
  • EXPANDED ERROR CORRECTION CODES
    Publication number: 20160085622
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on whether the majority of bits are set to a high state or a low state. For instance, the memory device may be configured to set each bit in the memory array to a low state when the data is read. The memory device may then be configured to store the data in the original state when a majority of the bits to be written to the array are in the low state and in the inverted state when the majority of the bits to be written to the array are in the high state.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventor: Thomas Andre
  • Word line auto-booting in a spin-torque magnetic memory having local source lines
    Patent number: 9286218
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 15, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • RESPONSE TO TAMPER DETECTION IN A MEMORY DEVICE
    Publication number: 20160070935
    Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Syed M. Alam, Thomas Andre
  • Non-destructive write/read leveling
    Patent number: 9275715
    Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 1, 2016
    Assignee: Everspin Technologies, Inc.
    Inventor: Thomas Andre
  • CIRCUIT AND METHOD FOR ACCESSING A BIT CELL IN A SPIN-TORQUE MRAM
    Publication number: 20160042781
    Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.
    Type: Application
    Filed: October 21, 2015
    Publication date: February 11, 2016
    Inventors: Syed M. Alam, Thomas Andre
  • CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES
    Publication number: 20160042780
    Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre
  • Assisted local source line
    Patent number: 9257165
    Abstract: In some examples, a memory device has a memory array configured to include sets of bit cells grouped based in part on an arrangement of local source lines. Each of the groups of cells may include an assist bit having a lower impedance than the other bit cells of the group to cause current distributed by the local source lines to be largely provided to the assist bit. In some examples, the assist bit include a shorted tunnel junction and in other examples, multiple assist bits may be connected by one or more bridge assisted bit lines.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 9, 2016
    Assignee: Everspin Technologies, Inc.
    Inventor: Thomas Andre
  • HYBRID READ SCHEME FOR SPIN TORQUE MRAM
    Publication number: 20160027489
    Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.
    Type: Application
    Filed: October 8, 2015
    Publication date: January 28, 2016
    Inventors: Syed M. Alam, Thomas Andre, Chitra Subramanian
  • Method of writing to a spin torque magnetic random access memory
    Patent number: 9245611
    Abstract: A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: January 26, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Matthew R. Croft, Chitra Subramanian, Halbert Lin
  • MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES
    Publication number: 20160019139
    Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
    Type: Application
    Filed: August 17, 2015
    Publication date: January 21, 2016
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
  • Word line driver circuit
    Patent number: 9230632
    Abstract: A word line driver circuit allows for dynamic selection of different word line voltages for selection and deselection of memory cells included in a resistive memory array in a manner that reduces circuit complexity, device count, and leakage currents.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: January 5, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Memory device with timing overlap mode
    Patent number: 9230633
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: January 5, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S Lin
  • Sensor Device, Filter Assembly, and Method for Manufacturing Same
    Publication number: 20150369788
    Abstract: A sensor device for a filter assembly is provided with at least one sensor element that detects an operating parameter of the filter assembly. A fire protection material at least partially encloses the sensor element. The sensor element is a water sensor. The fire protection material comprises an intumescent material.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 24, 2015
    Inventor: Thomas Andres
  • Response to tamper detection in a memory device
    Patent number: 9218509
    Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 22, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Self-referenced sense amplifier for spin torque MRAM
    Patent number: 9218865
    Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 22, 2015
    Assignee: Everspin Technologies, Inc
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
  • TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE
    Publication number: 20150356322
    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 10, 2015
    Inventors: Chitra K. Subramanian, Halbert S. Lin, Syed M. Alam, Thomas Andre
  • METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE
    Publication number: 20150355967
    Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 10, 2015
    Inventors: Syed M. Alam, Thomas Andre, Matthew R. Croft
  • Circuit and method for spin-torque MRAM bit line and source line voltage regulation
    Patent number: 9196342
    Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: November 24, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Hybrid read scheme for spin torque MRAM
    Patent number: 9183911
    Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 10, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Chitra Subramanian