Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE
    Publication number: 20090206316
    Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Applicant: Qimonda AG
    Inventors: Rolf Weis, Thomas Happ
  • Memory including write circuit for providing multiple reset pulses
    Patent number: 7577023
    Abstract: An integrated circuit includes an array of resistive memory cells having varying critical dimensions and a write circuit. The write circuit is configured to reset a selected memory cell by applying a first pulse having a first amplitude and a second pulse having a second amplitude less than the first amplitude to the selected memory cell.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: August 18, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ, Thomas Nirschl
  • METHOD FOR FABRICATION OF POLYCRYSTALLINE DIODES FOR RESISTIVE MEMORIES
    Publication number: 20090200534
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 13, 2009
    Applicants: IBM CORPORATION, MACRONIX INTERNATIONAL CO., LTD., QIMONDA AG
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
  • ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS
    Publication number: 20090199043
    Abstract: An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventors: Peter Schrogmeier, Jan Boris Philipp, Thomas Happ, Luca DeAmbroggi, Christian Pho Duc, Franz Kreupl, Gernot Steinlesberger
  • INTEGRATED CIRCUIT INCLUDING ELECTRODE HAVING RECESSED PORTION
    Publication number: 20090196094
    Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 6, 2009
    Inventors: Matthew Breitwisch, Shihhung Chen, Thomas Happ, Eric Joseph
  • STACKED DIE MEMORY
    Publication number: 20090196093
    Abstract: A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second die. The first die and the second die are enclosed in a single package.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Applicant: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS
    Publication number: 20090185411
    Abstract: The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 23, 2009
    Inventors: Thomas Happ, Chung Hon Lam, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Circuit for programming a memory element
    Patent number: 7564710
    Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: July 21, 2009
    Assignees: Qimonda North America Corp., Macronix International Co., Ltd.
    Inventors: Thomas Happ, Jan Boris Philipp, Ming-Hsiu Lee
  • METHOD FOR FABRICATION OF SINGLE CRYSTAL DIODES FOR RESISTIVE MEMORIES
    Publication number: 20090176354
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 9, 2009
    Applicants: International Business Machines Corporation, Qimonda North America Corporation, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION
    Publication number: 20090161415
    Abstract: An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ, Bernhard Ruf, Christian Ruster, Dieter Andres, Petra Majewski
  • OPTIMIZED PHASE CHANGE WRITE METHOD
    Publication number: 20090161416
    Abstract: A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Qimonda AG
    Inventors: Mark Lamorey, Thomas Happ
  • Resistive memory having shunted memory cells
    Patent number: 7551476
    Abstract: A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current divider with a selected memory cell during a read operation.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: June 23, 2009
    Assignees: Qimonda North America Corp., Qimonda AG
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS
    Publication number: 20090154227
    Abstract: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Inventors: Jan Boris Philipp, Thomas Happ
  • INTEGRATED CIRCUIT INCLUDING QUENCH DEVICES
    Publication number: 20090154226
    Abstract: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Applicant: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit having a switch
    Patent number: 7548448
    Abstract: A reprogrammable switch includes a first phase-change element, a first reference element, and a second reference element. The switch includes a sense amplifier for outputting a first signal based on a comparison of a signal from the first phase-change element to a signal from the first reference element and for outputting a second signal based on a comparison of the signal from the first phase-change element to a signal from the second reference element.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 16, 2009
    Assignee: Infineon Technologies AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated Circuit, and Method for Manufacturing an Integrated Circuit
    Publication number: 20090146131
    Abstract: According to one embodiment of the present invention, a method of manufacturing an integrated circuit including a plurality of memory cells is provided, including: forming a first isolation layer including a plurality of contact elements, each contact element extending from the top surface of the first isolation layer to the bottom surface of the first isolation layer; forming a second isolation layer on the first isolation layer, wherein the material of the first isolation layer is different from the material of the second isolation layer; forming trenches within the second isolation layer above the contact elements, wherein the trenches are formed using an etching substance which selectively etches the material of the second isolation layer over the material of the first isolation layer; and filling the trenches with resistivity changing material.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 11, 2009
    Inventor: Thomas Happ
  • INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT
    Publication number: 20090147563
    Abstract: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Inventors: Thomas Happ, Thomas Nirschl, Jan Boris Philipp
  • Mushroom phase change memory having a multilayer electrode
    Patent number: 7545668
    Abstract: An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: June 9, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated circuit including logic portion and memory portion
    Patent number: 7545019
    Abstract: An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: June 9, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ, Thomas Nirschl
  • Resistive memory including refresh operation
    Patent number: 7539050
    Abstract: A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 26, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ