Patents by Inventor Toshifumi Wakano

Toshifumi Wakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083266
    Abstract: A solid-state imaging element of a pixel sharing type with improved driving of transistors is disclosed. A first electric charge accumulating section and a second electric charge accumulating section are arranged in a predetermined direction. A first transfer section transfers electric charge from first photoelectric conversion elements to the first electric charge accumulating section, causing it to accumulate the electric charge. A second transfer section transfers electric charge from second photoelectric conversion elements to the second electric charge accumulating section, causing it to accumulate the electric charge. A first transistor is configured to output a signal corresponding to an amount of the electric charge accumulated in each of the first electric charge accumulating section and the second electric charge accumulating section. A second transistor is arranged with the first transistor in the predetermined direction and connected in parallel to the first transistor.
    Type: Application
    Filed: February 23, 2018
    Publication date: March 12, 2020
    Inventors: Kazuhiko Nakadate, Toshifumi Wakano, Masahiko Nakamizo
  • Publication number: 20200083265
    Abstract: A semiconductor device includes a plurality of pixels arranged in a two-dimensional array, each pixel of the plurality of pixels including a photoelectric conversion film configured to photoelectrically convert light of a first wavelength and pass light of a second wavelength, and a photoelectric conversion unit configured to photoelectrically convert the light of the second wavelength. The semiconductor device may further include a charge storage unit configured to store charge received from the photoelectric conversion unit of each pixel in a pixel group, wherein the pixel group includes adjacent pixels among the plurality of pixels, a plurality of through electrodes, and a wiring layer coupled to the photoelectric conversion film of each pixel of the plurality of pixels by at least one through electrode of the plurality of through electrodes. The present technology can be applied to a solid-state imaging element.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 12, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Toshifumi WAKANO
  • Patent number: 10586818
    Abstract: A solid-state imaging device includes a plurality of photoelectric conversion units, a floating diffusion unit that is shared by the plurality of photoelectric conversion units and converts electric charge generated in each of the plurality of photoelectric conversion units into a voltage signal, a plurality of transfer units that are respectively provided in the plurality of photoelectric conversion units and transfer the electric charge generated in the plurality of photoelectric conversion units to the floating diffusion unit, a first transistor group that is electrically connected to the floating diffusion unit and includes a gate and source/drain which are arranged with a first layout configuration, and a second transistor group that is electrically connected to the floating diffusion unit, includes a gate and source/drain arranged with a second layout configuration symmetrical to the first layout configuration, and is provided in a separate area from the first transistor group.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 10, 2020
    Assignee: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Atsuhiko Yamamoto
  • Patent number: 10580817
    Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 3, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Akira Matsumoto, Junpei Yamamoto, Ryusei Naito, Masahiko Nakamizo, Toshifumi Wakano
  • Patent number: 10546898
    Abstract: This technology relates to an imaging apparatus and an electronic device structured to perform pupil correction appropriately. There are provided a photoelectric conversion film configured to absorb light of a predetermined color component to generate signal charges, a first lower electrode configured to be formed under the photoelectric conversion film, a second lower electrode configured to be connected with the first lower electrode, a via configured to connect the first lower electrode with the second lower electrode, and a photodiode configured to be formed under the second lower electrode and to generate signal charges reflecting the amount of incident light. A first distance between the center of the photodiode and the center of the via at the center of the angle of view is different from a second distance therebetween at an edge of the angle of view. The present technology can be applied to imaging apparatuses.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventors: Yusuke Otake, Toshifumi Wakano
  • Patent number: 10535687
    Abstract: The present technology relates to a solid-state imaging device that can achieve a higher resolution while increasing sensitivity. In a pixel array unit, pixels are formed with a combination of a first pixel that performs photoelectric conversion on light of a first color component with a first photoelectric conversion unit, and photoelectric conversion on light of a third color component with a second photoelectric conversion unit; a second pixel that performs photoelectric conversion on light of the first color component with a first photoelectric conversion unit, and on light of a fifth color component with a second photoelectric conversion unit; and a third pixel that performs photoelectric conversion on light of the first color component with a first photoelectric conversion unit, and on light of a sixth color component with a second photoelectric conversion unit. The first color component and the sixth color component are mixed, to generate white (W).
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 14, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kenji Azami, Yusuke Otake, Toshifumi Wakano
  • Publication number: 20200006417
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 2, 2020
    Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
  • Publication number: 20190373163
    Abstract: The present disclosure relates to an image pickup device that enables inhibition of occurrence of color mixture or noise, and an electronic apparatus. The image pickup device of the present disclosure includes an image plane phase difference detection pixel for obtaining a phase difference signal for image plane phase difference AF.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kyohei YOSHIMURA, Toshifumi WAKANO, Yusuke OTAKE
  • Patent number: 10483313
    Abstract: There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventor: Toshifumi Wakano
  • Publication number: 20190348450
    Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Applicant: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano
  • Patent number: 10468438
    Abstract: A semiconductor device includes a plurality of pixels arranged in a two-dimensional array, each pixel of the plurality of pixels including a photoelectric conversion film configured to photoelectrically convert light of a first wavelength and pass light of a second wavelength, and a photoelectric conversion unit configured to photoelectrically convert the light of the second wavelength. The semiconductor device may further include a charge storage unit configured to store charge received from the photoelectric conversion unit of each pixel in a pixel group, wherein the pixel group includes adjacent pixels among the plurality of pixels, a plurality of through electrodes, and a wiring layer coupled to the photoelectric conversion film of each pixel of the plurality of pixels by at least one through electrode of the plurality of through electrodes. The present technology can be applied to a solid-state imaging element.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 5, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Toshifumi Wakano
  • Publication number: 20190326338
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Toshifumi WAKANO, Takuya SANO, Yusuke TANAKA, Keiji TATANI, Hideo HARIFUCHI, Eiichi TAUCHI, Hiroki IWASHITA, Akira MATSUMOTO
  • Patent number: 10446601
    Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode (105) and a cathode (101). The cathode is in a well region (103) of the first substrate. The first pixel includes an isolation region (108) that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region (107a) between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 15, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Akira Matsumoto, Junpei Yamamoto, Ryusei Naito, Masahiko Nakamizo, Toshifumi Wakano
  • Patent number: 10432844
    Abstract: The present disclosure relates to an image pickup device that inhibits color mixture or noise, and an electronic apparatus. The image pickup device of the present disclosure includes an image plane phase difference detection pixel for image plane phase difference AF. The image plane phase difference detection pixel includes: a first photoelectric conversion section; an upper electrode section that is one of electrodes disposed facing each other, the upper electrode section being formed on a light incident side first photoelectric conversion section; and a lower electrode section that is another of the electrodes disposed facing each other, the lower electrode section being formed on an opposite side of the first photoelectric conversion section, the lower electrode section being multiple-divided at a position that avoids a center of the incident light. The present disclosure is applicable to image sensors.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 1, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kyohei Yoshimura, Toshifumi Wakano, Yusuke Otake
  • Publication number: 20190267414
    Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Akira MATSUMOTO, Junpei YAMAMOTO, Ryusei NAITO, Masahiko NAKAMIZO, Toshifumi WAKANO
  • Patent number: 10396116
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: August 27, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
  • Publication number: 20190252442
    Abstract: An imaging device comprises a sensor substrate including a pixel array that includes at least a first pixel. The first pixel includes an avalanche photodiode including a light receiving region, a cathode, and an anode. The first pixel includes a wiring layer electrically connected to the cathode and arranged in the sensor substrate such that the wiring layer is in a path of incident light that exits the light receiving region.
    Type: Application
    Filed: November 15, 2017
    Publication date: August 15, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Akira TANAKA, Yusuke OTAKE, Toshifumi WAKANO
  • Patent number: 10381390
    Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 13, 2019
    Assignee: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano
  • Patent number: 10347673
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: July 9, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Toshifumi Wakano, Takuya Sano, Yusuke Tanaka, Keiji Tatani, Hideo Harifuchi, Eiichi Tauchi, Hiroki Iwashita, Akira Matsumoto
  • Publication number: 20190181177
    Abstract: An imaging device includes a first chip (12). The first chip includes a first pixel (21) and a second pixel (21). The first pixel includes a first anode region (31) and a first cathode region (32), and the second pixel includes a second anode region (31) and a second cathode region (32). The first chip includes a first wiring layer (23). The first wiring layer includes a first anode electrode (37), a first anode via (38) coupled to the first anode electrode (37) and the first anode region (31), and a second anode via (38) coupled to the first anode electrode (37) and the second anode region (31).
    Type: Application
    Filed: July 25, 2018
    Publication date: June 13, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kenji KOBAYASHI, Toshifumi WAKANO, Yusuke OTAKE