Abstract: A method and apparatus for detecting a planar endpoint on a semiconductor wafer during chemical/mechanical planarization of the wafer. The planar endpoint is detected by sensing a change in friction between the wafer and a polishing surface. This change of friction may be produced when, for instance, an oxide coating of the wafer is removed and a harder material is contracted by the polishing surface. In a preferred form of the invention, the change in friction is detected by rotating the wafer and polishing surface with electric motors and measuring current changes on one or both of the motors. This current change can then be used to produce a signal to operate control means for adjusting or stopping the process.

Abstract: A process for forming silicon nitride layers on silicon substrates which includes initially heating the silicon substrates in a rapid thermal processor and in a substantially oxygen-free and residual moisture free environment to form a thin Si.sub.3 N.sub.4 layer directly on the silicon surface which is free of any measurable native SiO.sub.2 thereon. Then, the nitridized wafers are transferred into a conventional nitride furnace where the thin Si.sub.3 N.sub.4 layers may be increased in thickness by a desired amount. Typically, the initial or first Si.sub.3 N.sub.4 layer thickness will be about 10-30 angstroms and the second Si.sub.3 N.sub.4 layer will be on the order of 80 angstroms or more to form a composite Si.sub.3 N.sub.4 layer of about 100-150 angstroms in total thickness.

Abstract: A method for improving step coverage of metallization layers of an aluminum alloy on an integrated circuit involves use of a deposited layer of a high melting point metal, such as tungsten or an alloy of tungsten and titanium, as an anti-reflective coating (ARC) to increase the efficient use of laser energy for planarization purposes where the underlying aluminum alloy covers a step, such as at an open via.

Abstract: An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete.

Abstract: A process for creating a metal etch mask from either cobalt, nickel, palladium, iron or copper which may be utilized for halogen-plasma excavation of deep trenches. The process begins by creating a thin isolation layer of either silicon nitride or silicon dioxide on top of the layer to be trenched. A thin layer of one of the metals selected from the aforementioned list of five is then created on top of the isolation layer. A layer of polysilicon is then blanket deposited on top of the refractory metal layer. Photoresist masking is then performed as though the photoresist were the actual pattern for the trench etch. Exposed portions of the polysilicon layer are then etched away with an anisotropic etch. Following a photoresist strip, the substrate and overlying layers are subjected to an elevated temperature step, which causes the polysilicon to react with the underlying metal layer to form metal silicide. In substrate regions where no polysilicon overlies the metal layer, no silicide is formed.

Abstract: Spaced-apart regions (2) each having top (2a) and side walls (2b) meeting at an edge (20) are defined on a surface (1a) of a substructure (1) forming part of the device. A layer (3) of insulating material is provided over the surface (1a) and regions (2), so that the insulating material is provided preferentially at the edges (20) of the regions (2) to form adjacent the edges (20) portions (31) of the insulating material which overhang the underlying insulating material (32) provided on the surface (1a) and define a void therein. The insulating material layer (3) is then etched anisotropically to expose the top walls (2a).

Abstract: An improved aluminum alloy from which interconnect lines of VLSI integrated-circuit devices may be fabricated. The alloy, which is comprised of aluminum, copper, titanium and silicon, is not only resistant to electromigration and stress cracking, but produces silicon precipitate crystals which are much finer that those produced by aluminum-copper-silicon alloys under the hot-and-cold temperature cycling that is required by contemporary semiconductor fabrication processes. These fine silicon precipitate crystals are much less likely to destroy the electrical continuity of an alloy-to-silicon junctions within an integrated-circuit device, even where dimensions of such junctions have been reduced. Although other alloy proportions are usable, optimal alloy percentages are deemed to be 0.5 to 3 percent copper by weight and 0.

Abstract: A bit-serial division method for computing the value v/u, where v and u are each n-bit vectors that are elements in a finite Galois field GF(2.sup.n) consisting of 2.sup.n elements. The n-bit components of each element in the field are coordinates of the element in a canonical basis of the field. Vector u is converted from canonical basis to a dual basis. Vector u in dual basis also comprises n bits in the finite field ordered according to an index i that takes on values from 0 to (n-1). All bits n of the converted vector u are loaded into a shift register in parallel, then converted from dual basis back to canonical basis to produce a single bit output w.sub.0 from a lookup table which generates bitwise the inverse of the n-bit vector u. The bits in the shift register are shifted (n-1) times to generate successive additional single bit outputs w.sub.i with said lookup table. Then each bit w.sub.i is multiplied by the vector v and a corresponding element c.sub.

Abstract: Disclosed is a method of etching back a tungsten layer on a semiconductor wafer by a polishing process. The method comprises:exposing the wafer to be polished to a polishing solution at a preselected temperature, the polishing solution comprising an oxidizing component which oxidizes tungsten on the wafer to tungsten oxide;mechanically polishing the tungsten oxide from the wafer and into the polishing solution; andthe polishing solution also comprising a dissolution component selected from the group consisting of KOH and NH.sub.4 OH or a mixture thereof, the tungsten oxide being substantially dissoluted by the dissolution component in the solution.

Abstract: A urethral inserted applicator for prostate hyperthermia includes a multi-tube, balloon type catheter. The catheter includes first and second closed end fluid dry tubes, respectively, for a helical coil antenna type applicator, and a microwave type temperature sensor for measuring the temperature of the prostate tissue, and an open fluid receiving tube. A microwave generator supplies electromagnetic energy to the applicator. A comparator is connected to the temperature sensor and a temperature reference potentiometer for comparing the actual tissue temperature level with a desired temperature level and outputting control signals to the microwave generator for controlling the output to the applicator. The coil type applicator is an elongated coil having a tip end connected to the center conductor of a coaxial cable and an opposite end connected to the outer conductor of the coaxial cable.

Abstract: A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the isolating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.

Abstract: A rechargeable electrochemical cell with an electrolyte and anode has a cathode including an active cathode material with a surface at which at least one side reaction occurs during a normal discharge cycle of the cell. The outer surface of the cathode material includes a protective coating that inhibits the side reactions without preventing discharge of the cathode.

Abstract: Disclosed is an electrochemical cell that includes an anode, a cathode, and an electrolyte, the cathode containing more than a trace amount of a sulfur impurity capable of causing the cell to self-discharge and also containing a scavenger that reacts with the impurity to reduce the rate of self-discharge of the cell.

Abstract: A shampoo composition contains in an aqueous carrier a quaternized polymer and a detergent.

Abstract: A main pump (rotary vane pump 1) and a secondary pump (radial piston pump 2) are driven by way of a common shaft (3), a cam ring (30) being used to drive the secondary pump. The cam ring is coupled to the shaft (3) by way of a shear pin (33). If the auxiliary pump locks, the shear pin fractures and the cam ring (30) can rotate relative to the shaft (3). In that case, the fracture portions of the shear pin (33) are driven into their respective bores (34, 35), thereby avoiding excessive friction and overheating. Therefore, the main pump can continue to operate in spite of the failure of the auxiliary pump.

Abstract: Aluminum capacitor foil is etched by passing it through a bath of electrolyte under the influence of pulsed direct current. The pulse duration is at least nine times as long as the interval between pulses when the current falls to zero and is preferably 3 to 27 milliseconds. The pulse current density is 2 to 10 A/in.sup.2, etching temperature is 50.degree. to 90.degree. C., and the electrolyte is an aqueous solution containing sodium chloride and sodium sulfate.

Abstract: Aluminum capacitor foil which has been etched for low-voltage applications is rendered usable in intermediate to high voltage capacitors by anodizing the foil in two-stages; first a low voltage stage in an adipate electrolyte and then a higher voltage stage in a borate electrolyte. The fine etch structure of the low-voltage etch is thereby not plugged in the second, higher voltage formation stage, whereby the foil is suitable for intermediate to high-voltage capacitor use.

Abstract: In the production of low voltage aluminum foil capacitor electrodes, etched and clean foil is subjected to a thermal treatment at about 595.degree. to 650.degree. C. and then anodized in an adipate formation electrolyte. The electrolyte may contain a minor amount of a phosphate salt, or the final reanodization may be carried out in a phosphate electrolyte.

Abstract: A hair dye or hair bleaching composition contains in an aqueous carrier a quaternized polymer.

Abstract: Aluminum electrolytic capacitor foil is treated after etching but before anodizing by first contacting it with a phosphate solution and then heat treating for 30 to 90 seconds to form a thermal oxide layer of controlled thickness. On subsequent anodization, the thermal oxide layer modifies the barrier oxide layer increasing its dielectric strength and hence capacitance and also stabilizes the barrier oxide layer.