Abstract: A transceiver has a transmitter portion using serially coupled FETs coupled o low level positive and negative bias sources to enable a low power drain conversion of TTL input signals to low level serial data output signals for a coaxial data transmission cable and vice versa The transceiver also provides a constant 50 ohm impedance for the coaxial or triaxial transmission cable during active transmission periods, stand-by periods and power-off periods to provide an inexpensive method to transmit and receive 10 Megabit coded data via a coaxial or triaxial cable.

Abstract: A method and apparatus for selectively oxidizing carbon monoxide in a hydrogen rich feed stream. The method comprises mixing a feed stream consisting essentially of hydrogen, carbon dioxide, water and carbon monoxide with a first predetermined quantity of oxygen (air). The temperature of the mixed feed/oxygen stream is adjusted in a first the heat exchanger assembly (20) to a first temperature. The mixed feed/oxygen stream is sent to reaction chambers (30,32) having an oxidation catalyst contained therein. The carbon monoxide of the feed stream preferentially absorbs on the catalyst at the first temperature to react with the oxygen in the chambers (30,32) with minimal simultaneous reaction of the hydrogen to form an intermediate hydrogen rich process stream having a lower carbon monoxide content than the feed stream. The elevated outlet temperature of the process stream is carefully controlled in a second heat exchanger assembly (42) to a second temperature above the first temperature.

Abstract: A process for depositing a thin film of aluminum nitride (AlN) includes sputtering an aluminum target with energetic nitrogen ions generated in a nitrogen plasma. A single gas (i.e. nitrogen) is used as both the reactive gas and as the sputtering gas. The process is especially adapted for forming an etchstop layer for use in forming contact vias through a dielectric layer in semiconductor manufacture. The process is also useful in semiconductor manufacture for forming an aluminum nitride (AlN) film that may be used as a passivation layer, as a ceramic packaging material, as a mask for ion implantation, as a substrate material in hybrid circuits, and as a high bandgap window for GaAs solar cells.

Abstract: A constant flow rate control valve (10) is provided including a cup member (12) disposed in a flow passage through the valve (10). The cup member has an orifice (18) located in an end wall (14) of the cup member (12) and a plurality of side ports (22) in a side wall (16) of the cup member (12) The cup member (12) is moveable axially within the-valve (10), with such movement being opposed by a resilient spring member (30) downstream of the cup member (12). The valve (10) includes a fixed retainer ring (26) in a valve body (24) surrounding the side wall (16) of the cup member (12) which blocks or exposes areas of the side ports (22) in response to movement of the cup member (12). Start up slots (34) in a side wall (36) of the valve body (24) are also blocked or exposed in response to movement of the cup member (12).

Abstract: A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.

Abstract: Disclosed is a chemical vapor deposition method of providing a conformal layer of TiN atop a semiconductor wafer in a manner which increases density and reduces etch rate of the TiN layer. The method comprises: a) positioning a wafer within a chemical vapor deposition reactor; b) heating the positioned wafer to a selected processing temperature of from about 200.degree. C. to about 600.degree. C.; c) injecting selected quantities of a gaseous titanium organometallic precursor of the formula Ti(NR.sub.2).sub.

Abstract: A LPCVD method for depositing a film of TiN on a semiconductor structure includes reacting an organometallic titanium source gas such as TMAT and organic silane as a reactive gas. The deposited film is a mixed phase of TiN and TiSi.sub.2 and is characterized by a low contact resistance, good step coverage and good barrier properties. The reaction is preferably carried out in a cold wall CVD reactor at relatively low temperatures (i.e. 200.degree. C.) and at pressures of from about 0.05 to 30 Torr.

Abstract: A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in recessed plugs which are not easily or reliably coupled with subsequent layers of sputtered aluminum or other conductors. The inventive process uses a two-step chemical mechanical planarization technique. An insulation layer with contact holes is formed, and a metal layer is formed thereover. A polishing pad rotates against the wafer surface while a slurry selective to the metal removes the metal overlying the wafer surface, and also recesses the metal within the contact holes due to the chemical nature and fibrous element of the polishing pad. A second CMP step uses a slurry having an acid or base selective to the insulation material to remove the insulator from around the metal.

Abstract: A dynamic random access memory (DRAM) cell having a corrugated storage contact capacitor for enhancing capacitance. A noncritical alignment is effected between the substrate contact area and the lower capacitor plate by using an etch stop layer to protect wordlines, field-effect transistors (FETs), and field oxide regions during the patterning and etching of storage capacitor regions. The corrugated storage contact capacitor is fabricated by depositing alternating layers of dielectric materials having either substantially different etch rates or wet etch selectivity one toward the other. The layers are isotropically etched and a cavity having corrugated sidewalls is provided. A doped poly layer is deposited to function as the storage-node capacitor plate. The deposition of a dielectric layer is followed by an insitu-doped poly layer deposited to form the upper capacitor plate. The capacitor thus formed is typified as having the storage-node capacitor plate self-aligned to the contact area of the substrate.

Abstract: Disclosed is a chemical vapor deposition (CVD) method of providing a conformal layer of titanium silicide atop a semiconductor wafer within a chemical vapor deposition reactor. Such includes, a) positioning a wafer within the CVD reactor; b) injecting selected quantities of gaseous TiCl.sub.4, a gaseous compound of the formula Si.sub.n H.sub.2n+2 where "n" is an integer greater than or equal to 2, and a carrier gas to within the reactor; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the TiCl.sub.4 and Si.sub.n H.sub.2n+2 to deposit a film on the wafer, the film comprising a titanium silicide.

Abstract: A method for forming silicides while simultaneously activating underlying silicon substrate active regions eliminates the need for separate annealing of the active region following ion-implantation procedures. The required energy for such simultaneous processing is provided by laser irradiation directed to the surface of a wafer after blanketing it with a layer of the metal desired in the silicide.

Abstract: An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.

Abstract: A method and apparatus for improving planarity of chemical mechanical planarization of semiconductor wafers. The wafer is affixed to the planar surface of a wafer carrier. A planar platen, on which is mounted a polishing pad, is moved about in a plane parallel to the pad surface with either an orbital, fixed-direction vibratory, or random-direction vibratory motion. In one embodiment of the invention, pressure between the surface of the wafer to be polished and the moving polishing pad is generated by the force of gravity acting on at least the wafer and the carrier; in another it is provided by a mechanical force applied normal to the wafer surface. The polishing pad is wetted with a slurry having abrasive particles suspended in a liquid which may be chemically reactive with respect to at least one material on the wafer.

Abstract: Fabrication of spacer supports for use in flat panel displays through a process which involves 1) depositing an insulating material on an electrode plate, 2) optionally, patterning a reflective material superjacent the insulating material, 3) irradiating the electrode plate, and thereby removing the exposed insulating material, 4) optionally, removing the reflective material, and thereby exposing the remaining insulative material which will serve as the spacer supports, after which the plate can be aligned with a complementary electrode plate, and a vacuum formed therebetween.

Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

Abstract: A semiconductor processing method of chemical mechanical polishing a predominately copper containing metal layer on a semiconductor substrate includes, a) providing a chemical mechanical polishing slurry comprising H.sub.2 O, a solid abrasive material, and a third component selected from the group consisting of HNO.sub.3, H.sub.2 SO.sub.4, and AgNO.sub.3 or mixtures thereof; and b) chemical mechanical polishing a predominately copper containing metal layer on a semiconductor substrate with the slurry. Such slurry also constitutes part of the invention. Such slurry may also contain an additional oxidant selected from the group consisting of H.sub.2 O.sub.2, HOCl, KOCl, KMgO.sub.4 and CH.sub.3 COOH or mixtures thereof to form a copper oxide passivating-type layer at the copper surface.

Abstract: A gettering process for semiconductor manufacturing is disclosed. The gettering process is performed after device formation and after a protective layer such as (BPSG) or (PSG) has been applied to the front side of a semiconductor wafer. The gettering process includes thinning and roughening a backside of the wafer using chemical mechanical planarization (CMP). During the (CMP) dislocations are formed which function as a trap of mobile contaminants. Additionally a gettering agent such as phosphorus is deposited and diffused into the backside of the wafer. The wafer can then be annealed for driving in the gettering agent and segregating mobile contaminants in the wafer at gettering centers formed at the dislocations and at gettering agent sites within the wafer crystal structure. The annealing step may also function to reflow and planarize the (BPSG) or (PSG) protective layer.

Abstract: This invention relates to a method for roughening a silicon or polysilicon substrate of a semiconductor. The method includes the steps of: depositing a metal layer onto the substrate, heating the metal layer and substrate through to form a metal silicide on the substrate by reaction of the metal layer and substrate, and removing the metal silicide and a metal oxide by selective etching to expose the roughened surface. The actual etching process may be a two-step procedure. A first etch uses ammonium hydroxide and hydrogen peroxide to remove the oxide layer formed with the silicide. A second etch uses hydrofluoric acid to remove the silicide.

Abstract: A local oxidation of silicon (LOCOS) process for semiconductor manufacture in which a barrier layer for the oxidation process and for a subsequent field implant is formed of a ceramic material. The ceramic material is one that can be easily deposited on silicon with low stress and is characterized by an ion stopping power greater than that of silicon nitride. Suitable ceramic materials include metal oxides, titanates, carbides, glasses and ferroelectrics.

Abstract: A semiconductor processing method of chemical mechanical polishing an aluminum containing metal layer on a semiconductor substrate includes, a) providing a chemical mechanical polishing slurry comprising H.sub.3 PO.sub.4 at from about 0.1% to about 20% by volume; H.sub.2 O.sub.2 at from about 1% to about 30% by volume, H.sub.2 O, and a solid abrasive material; and b) chemical mechanical polishing an aluminum containing metal layer on a semiconductor substrate with the slurry. Such process and slurry are also usable in chemical mechanical polishing of other layers, such as Ti, TiN and TiW materials. Such enables chemical mechanical polishing of a barrier metal/aluminum layer composite in a single polishing step, leading to increased controllability and resulting increased throughput. With respect to aluminum containing metal layers, the H.sub.2 O.sub.2 is understood to cause oxidation to aluminum oxide, which is subsequently removed by both chemical and mechanical action the result of the polish and slurry.