Abstract: An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Abstract: The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

Abstract: A driver circuit has a single feedback transistor in the driver transistor well to provide a momentary feedback from source to gate and maintain conductance of the driver transistor during turnoff of the driver transistor and thus reduce ringing oscillation at the transistor source output. An enable/disable signal is applied to control conduction circuitry and the driver transistor and force the output to a high impedance state when the circuit is disabled. Clocked operation of the driver circuit is provided with circuitry merged with a latch. A terminal for receiving a global i.sub.dd test signal controls circuitry removing power to the driver circuit and applying a ground potential to the driver output in response to the global i.sub.dd test signal.

Abstract: An improved internal line up clamp (10) is disclosed which has an integral back up ring (12). A first set of pipe clamps (22) move radially outward to engage the inner surface of a first pipe (14). A second set of pipe clamps (62) and a set of back up ring segments (202) are simultaneously moved radially outward into engagement with the inner surface of the pipes. The back up ring segments (202) are spring loaded to exert a relatively constant back up force against the inner surface of the pipes at the weld. The back up ring segments support the shoe elements (220). The shoe elements are spring loaded to accommodate diameter mismatch and non-circularity of the pipe ends. The back up ring segments rotate about a radial axis from the pipe centerline. Tapered ends on the back up ring segments provide for the decrease in ring circumference necessary to lower the ring segments.

Abstract: A method for making self aligned rim phase shifting masks for photolithography is provided. The method includes providing a transparent substrate (e.g., quartz) having a patterned opaque layer (e.g., chrome) and then forming phase shifters at the rim or edges of the features defined by the opaque layer. The phase shifters are formed by depositing two different layers of transparent material (e.g., Si.sub.3 N.sub.4 /SiO.sub.2) over the substrate and opaque layer. The first layer of material is a spacer layer which accurately spaces the rim phase shifters from the feature. The second layer of material is a phase shifter layer that forms the bulk of the rim phase shifters. Following deposition both layers are planarized to expose the spacer layer. The spacer layer is then selectively etched with respect to the phase shifter layer. This is followed by another etch of the phase shifter layer to form the rim phase shifters.

Abstract: A method of chemically-mechanically planarizing (CMP) a dielectric layer formed on semiconductor wafer includes planarizing the dielectric layer with a polishing pad formed of a hard low compressibility pad material, and then polishing the dielectric layer with a polishing pad formed of a soft compressible pad material to remove micro-scratches formed during the planarization step. During the planarization step, the hard low compressibility pad material does not deform into the surface of the dielectric layer and the dielectric layer is planarized along a single contact plane. A loading effect in which the a material compresses and produces an irregular surface is thus eliminated.

Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber.

Abstract: A system for polishing a semiconductor wafer includes a rotatable platen subassembly and a drive mechanism coupled to rotate the platen subassembly at a platen velocity. A polishing head supports and holds a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face whereby individual regions of the wafer face have different polishing rates. The polishing head includes pressure applicators for applying various localized pressures on the individual regions of the semiconductor wafer to conform the wafer face to a selected contour. The system also includes a polish control subsystem for monitoring in situ the polishing rates at various regions of the semiconductor wafer. The polish control subsystem adjusts in situ the platen velocity and/or the individual localized pressures applied to the semiconductor wafer to change the polishing rates of the individual regions of the semiconductor wafer.

Abstract: A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing.

Abstract: A CMOS tri-state driver circuit is capable of operating in a normal drive mode and in a high impedance mode. The circuit is powered by a 3 volt power supply, and drives an output terminal that is common to a TTL or other device that can apply a 5 volt output to the output terminal. The circuit includes a PMOS pull-up transistor and an NMOS pull-down transistor that are connected to the output terminal. The pull-up transistor is formed in and has a substrate terminal that is connected to an N-well. A switching transistor is controlled to connect the N-well to the power supply in drive mode to ensure stable and strong pull-up drive. A pass-gate transistor is biased to turn off the switching transistor when the voltage at the output terminal is higher than the power supply voltage in high impedance mode, causing the N-well to float. This prevents leakage current from flowing through a semiconductor junction from the output terminal to the N-well through the pull-up transistor.

Abstract: A system and an associated method for determining a solution to a problem using on-line documentation. The system includes a processor-based intelligent search engine and an associated questionless case-based knowledge base which contains a series of questionless case structures, each comprised of a title, a description of a particular problem and a solution to the particular problem, stored in memory.

Abstract: A semiconductor processing method of detecting polishing end point in a chemical-mechanical polishing planarization process includes the following steps: a) chemical-mechanical polishing an outer surface of a semiconductor substrate using a chemical-mechanical polishing pad; b) during such chemical-mechanical polishing, measuring sound waves emanating from the chemical-mechanical polishing action of the substrate against the pad; c) detecting a change in the sound waves as the surface being chemical-mechanical polished becomes substantially planar; and d) ceasing chemical-mechanical polishing upon detection of the change. Alternately instead of ceasing chemical-mechanical polishing, a mechanical polishing process operational parameter could be changed upon detection of the change and then continuing mechanical polishing with the changed operational parameter. In another aspect of the invention, first and second layers to be polished are provided on a semiconductor wafer.

Abstract: A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.

Abstract: An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.

Abstract: A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material removed through the sputter etch process is oxidized and redeposited along the sides of the feature and along the surface of the substrate, thereby improving step coverage when a subsequent dielectric layer is deposited thereon.

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver invertor having an input and an output. The invertor inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regi

Abstract: The present invention relates to a process of making a concentrate of coagulation proteins starting with whole human or animal plasma. This concentrate is used as a biological adhesive when extemporaneously mixed to thrombin. The concentrated proteins include mostly fibrinogen, fibrin stabilizing factor (factor XIII) and fibronectin. The claimed process has the advantage of being short of execution while providing an excellent yield of coagulable proteins. No protease inhibitor has to be added during the process. The process involves steps of separation by "salting-out" in presence of amino-6 hexanoic acid which prevents co-precipitation of plasminogen with the desired coagulable proteins. The proteins so obtained are very stable after reconstitution in water for at least 24 hours at room or body temperature. After mixing with thrombin and calcium, the adhesive shows excellent strength and biocompatibility.

Abstract: A semiconductor processing method of providing and planarizing an insulating layer on a semiconductor wafer includes the following sequential steps: a) providing a conformal layer of insulating material to a first thickness over a semiconductor wafer having non-planar topography; b) providing a CMP polishing protective layer over the conformal layer to a second thickness, the protective layer being of different composition than the conformal layer; and c) chemical-mechanical polishing the protective layer and conformal layer in a single CMP step using a single CMP slurry and under conditions which in combination with the slurry remove the conformal layer material at a faster rate than the protective layer material, the protective layer upon outward exposure of conformal layer material in high topographical areas restricting material removal from low topographical areas during such chemical-mechanical polishing.

Abstract: A semiconductor processing includes: a) providing an area atop a semiconductor wafer to which electrical connection to a polysilicon containing component is to be made; b) providing a layer of first material atop the semiconductor wafer, the first material layer having an upper surface; c) providing a contact opening in the layer of first material to the area, the contact opening having a selected open cross dimension; d) providing a layer of polysilicon to a selected thickness atop the layer of first material and within the contact opening to contact the area, the selected thickness being less than one-half the open dimension such that polysilicon less than completely fills the contact opening and thereby defines an outwardly open polysilicon lined cavity; e) with the wafer having the polysilicon lined cavity outwardly open, chemical mechanical polishing with a chemical mechanical polishing slurry the polysilicon atop the first material layer to the upper first material layer surface to define an isolated po