Patents by Inventor Trung (Tim) Trinh
Trung (Tim) Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5205770Abstract: Fabrication of spacer supports for use in field emitter displays through a process which involves 1) forming a mold for the spacers in a substrate through the use of micro-saw technology, 2) filling the mold with a material that is selectively etchable with respect to the mold, 3) optionally, planarizing the excess material to the level of the mold using chemical mechanical planarization, 4) attaching the filled mold to one of the electrode plates of the field emitter display, and 5) etching away (removing) the mold, after which 6) the plate can be aligned with its complementary electrode plate, and 7) a vacuum formed.Type: GrantFiled: March 12, 1992Date of Patent: April 27, 1993Assignee: Micron Technology, Inc.Inventors: Tyler A. Lowrey, Trung T. Doan, David A. Cathey, J. Brett Rolfson
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Patent number: 5206187Abstract: A method of processing a semiconductor wafer comprises: a) fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations of the wafer; b) providing a layer of transition metal oxide elevationally above the active regions; c) applying an insulating dielectric layer elevationally above the transition metal oxide layer; d) etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and e) etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.Type: GrantFiled: December 17, 1991Date of Patent: April 27, 1993Assignee: Micron Technology, Inc.Inventors: Trung T. Doan, Gurtej S. Sandhu
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Patent number: 5204286Abstract: A process for making vertical electrical interconnections in a variety of integrated circuits and novel IC structures produced thereby wherein buried conductors are provided within a dielectric layer located above a silicon substrate having active or passive devices formed therein. Internal edges of only one or selected ones of the conductors are provided with an insulating coating, so that an adjacent via may be filled with a conductive material and still be electrically isolated from the one conductor or conductors. One or more vias are etched directly through the other buried conductor or conductors and also filled with a conductive material which electrically connects this buried conductor or conductors to both the substrate and to an upper level of metallization, and alternatively to intermediate conductors or other components.Type: GrantFiled: October 15, 1991Date of Patent: April 20, 1993Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 5202278Abstract: A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590.degree. and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm.sup.2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.Type: GrantFiled: September 10, 1991Date of Patent: April 13, 1993Assignee: Micron Technology, Inc.Inventors: Viju K. Mathews, Chang Yu, Mark E. Tuttle, Trung T. Doan
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Patent number: 5196353Abstract: A method and apparatus for controlling a chemical mechanical planarization (CMP) process in semiconductor manufacture includes an infrared camera for detecting and mapping a temperature of the wafer for developing a thermal image of the wafer. The thermal image can then be analyzed and used to control the operational parameters of the (CMP) process such as time, temperature, and downward pressure, in order to enhance the uniformity of polishing across the wafer. In addition, it can be used to end-point the (CMP) process by detecting sudden changes in the wafer surface temperature as one layer is completely polished away exposing an underlying layer of a different material.Type: GrantFiled: January 3, 1992Date of Patent: March 23, 1993Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Trung T. Doan
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Patent number: 5196360Abstract: The present invention is directed to methods for preparing silicide contact areas on integrated circuit devices which inhibit outgrowth of silicide and formation of potential short circuit paths between adjacent silicide contact areas. This may be achieved by depositing a nitrogen-rich titanium nitride layer over the conventional titanium layer prior to silicidation. In those regions on the integrated circuit device where titanium is deposited on spacer oxide regions separating adjacent silicide contact areas, excess nitrogen from the nitrogen-rich titanium nitride layer reacts with the titanium film to form titanium nitride. The final structure after silicidation contains titanium silicide contact areas separated by titanium nitride regions. The titanium nitride regions inhibit outgrowth of titanium silicide from the silicide contact areas. After silicidation, excess titanium nitride and titanium may be removed by etching.Type: GrantFiled: April 6, 1992Date of Patent: March 23, 1993Assignee: Micron Technologies, Inc.Inventors: Trung T. Doan, Gurtej S. Sandhu
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Patent number: 5191337Abstract: A maximum likelihood estimator and range-only-initialization target detection method employed to detect and resolve targets in a multislope linear frequency modulated waveform radar. The method resolves a large number of target returns without a large amount of signal processing and without creating a significant number of false alarms, or ghosts. The method simultaneously estimates range and doppler for each target. The method rejects undesired long-range targets that fold into target regions, and processes target regions of interest around a nearest target to reduce signal processing throughput requirements. Using a K out of N detection rule, the method detects targets that compete with mainlobe rain clutter, mainlobe ground clutter, and receiver leakage. The method simultaneously estimates target parameters and optimally resolves any number of targets.Type: GrantFiled: February 25, 1992Date of Patent: March 2, 1993Assignee: Hughes Aircraft CompanyInventors: Oleg Brovko, Trung T. Nguyen
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Patent number: 5186670Abstract: A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.Type: GrantFiled: March 2, 1992Date of Patent: February 16, 1993Assignee: Micron Technology, Inc.Inventors: Trung T. Doan, Tyler A. Lowrey, David A. Cathey, J. Brett Rolfson
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Patent number: 5174330Abstract: A constant flow rate control valve (10) is provided including a cup member (12) disposed in a flow passage through the valve (10). The cup member has an orifice (18) located in an end wall (14) of the cup member (12) and a plurality of side ports (22) in a side wall (16) of the cup member (12). The cup member (12) is moveable axially within the valve (10), with such movement being opposed by a resilient spring member (30) downstream of the cup member (12). The valve (10) includes a fixed retainer ring (26) in a valve body (24) surrounding the side wall (16) of the cup member (12) which blocks or exposes areas of the side ports (22) in response to movement of the cup member (12). Start up slots (34) in a side wall (36) of the valve body (24) are also blocked or exposed in response to movement of the cup member (12).Type: GrantFiled: December 5, 1991Date of Patent: December 29, 1992Assignee: Flow Design, Inc.Inventors: Farhad Golestan, Trung K. Pham, David I. Sexton, Jr.
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Patent number: 5173441Abstract: A semiconductor manufacturing process for laser ablation deposition (LAD) in which metal features are written from a source substrate onto a target substrate. The source substrate and target substrate are mounted in close proximity to one another within a vacuum chamber. A laser beam is scanned in a programmed sequence or selected pattern through a transparent target substrate and onto a metallic film formed on the source substrate. Ablation of the metal film and deposition onto the target substrate may be closely controlled by the laser being focused directly at the metal film on the source substrate and by the selection of a source substrate having a suitable thermal conductivity. The process may be further controlled by selective heating of the source substrate. The process can be used to ablate and deposit a single or multiple metal layers on the target substrate.Type: GrantFiled: February 8, 1991Date of Patent: December 22, 1992Assignee: Micron Technology, Inc.Inventors: Chang Yu, Trung T. Doan
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Patent number: 5173327Abstract: The present invention describes a CVD process to deposit a titanium film at a high deposition rate that has excellent uniformity and step coverage while avoiding gas phase nucleation and coating of the reactor chamber walls. The vapor of a heated liquid titanium source enters a modified, plasma enhanced, cold wall reaction chamber and is mixed with H.sub.2 as it reaches a wafer substrate surface. As the gas vapors reach the heated wafer substrate a chemical reaction of TiCl.sub.4 +2H.sub.2 .fwdarw.Ti+4HCl is triggered, thereby depositing a uniform titanium film upon the substrate surface. The deposition rate is further enhanced by the presence of rf plasma above the substrate's surface.Type: GrantFiled: June 18, 1991Date of Patent: December 22, 1992Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Trung T. Doan
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Patent number: 5169491Abstract: A method of planarizing SiO.sub.2 containing dielectric in semiconductor wafer processing comprising: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) depositing a layer of borophosphosilicate glass atop the layer of undoped SiO.sub.2 ; and c) chemical mechanical polishing the borophosphosilicate glass layer selectively relative to the underlying layer of undoped SiO.sub.2 layer and using the layer of undoped SiO.sub.2 as an effective chemical mechanical polishing end-point etch stop to prevent further etching of the borophosphosilicate glass and produce a substantially planar upper wafer surface of dielectric.Type: GrantFiled: July 29, 1991Date of Patent: December 8, 1992Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 5147819Abstract: A method of applying an alloy layer of predetermined thickness on a semiconductor wafer to fill contact openings having a defined diameter, the method comprising the following steps:chemical vapor depositing (CVD) a layer of elemental metal atop the wafer to a thickness of from 5% to 35% of the defined contact diameter;sputtering a layer of an alloy atop the chemical vapor deposited layer of elemental metal to a thickness which results in the combination of the chemical vapor deposited and sputtered layers having substantially the predetermined overall layer thickness; andcombining and intermixing the sputtered alloy layer with the chemical vapor deposited elemental metal layer to form an overall homogenous alloy layer by applying energy to the sputtered alloy layer, the application of energy also filling contact openings and planarizing the homogenous layer.Preferably, the CVD layer has a thickness of from 10% to 20%, and the energy is applied by a scanning pulsed laser.Type: GrantFiled: February 21, 1991Date of Patent: September 15, 1992Assignee: Micron Technology, Inc.Inventors: Chang Yu, Trung T. Doan, Gurtej S. Sandhu
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Patent number: 5139967Abstract: A method of processing a semiconductor wafer comprises the following sequential steps:selectively fabricating a semiconductor wafer in multilevels to produce desired electronic devices and integrated circuits on the wafer, the selective fabrication resulting in an irregular upper surface topography;applying a coating of insulating dielectric material having a melting point of less than or equal to about 850.degree. C. atop the fabricated wafer; andselectively impinging laser energy upon the dielectric coating for a selected period of time to at least partially melt the dielectric coating and cause its upper surface to become planarized.Type: GrantFiled: February 20, 1991Date of Patent: August 18, 1992Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Trung T. Doan, Chang Yu
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Patent number: 5136362Abstract: A device is provided by forming a diffusion barrier at the interface between a metalized contact and the surface of a semiconductor substrate. A three-layer sandwich is formed over the contact region and then annealed in free nitrogen. The sandwich is made of a titanium nitride layer interposed between layers of titanium. During the anneal, material from the titanium layer adjacent to the substrate migrates thereinto to produce a highly conductive diffusion region of titanium silicide. Concurrently during the anneal the other layer of titanium, which is exposed to the nitrogen atmosphere, is converted into a backing layer of titanium nitride which enhances the barrier effect of the titanium nitride layer at the center of the sandwich structure. The conversion of titanium to titanium nitride causes a physical expansion in the layer involved. This serves to enhance the thickness of the barrier layer at all locations, but of particular significance at the corners of the contact well.Type: GrantFiled: November 27, 1990Date of Patent: August 4, 1992Inventors: Malcolm K. Grief, Trung Doan
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Patent number: 5132236Abstract: A process for fabricating a CMOS integrated circuit having both P-channel and N-channel areas in the substrate. The process forms a single self-aligned mask to define the positions of both of the channel areas on the substrate. The process includes: depositing a maskable material on the substrate; photopatterning and etching the maskable material to expose a pattern of areas on the substrate; tailoring the pattern of areas as P-channel or N-channel; depositing a second material over the maskable material and over the tailored areas of the substrate; chemically mechanically polishing (CMP) the second material to an endpoint of the maskable material; selectively etching the maskable material to expose a second pattern of areas on the substrate aligned with the first pattern of areas; and then tailoring the second pattern of areas as P-channel or N-channel.Type: GrantFiled: July 30, 1991Date of Patent: July 21, 1992Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 5124780Abstract: The invention is a method of forming a conductive contact plug and an interconnect line independent of each other. The contact plug is formed using laser planarization and a blanket etch back. The invention is also the contact plug thus formed. The contact plug and interconnect line may be fabricated with conductive materials having substantially similar methods of deposition. The integrity of the contact plug is enhanced using laser planarization.The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. A masking step defines a contact hole. An etch creates the contact hole which passes through the dielectric layer to a conductive region where contact is to be made. A first layer of conductive material is then deposited overlying the dielectric layer. A layer of material having an anti-reflective coating (ARC) (or a layer of material having a higher boiling point than the first layer) is deposited overlying the first layer.Type: GrantFiled: June 10, 1991Date of Patent: June 23, 1992Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Chang Yu, Trung T. Doan, Mark E. Tuttle
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Patent number: 5094977Abstract: A method of processing a semiconductor wafer comprises, a) chemical vapor depositing (CVD) a metal layer atop a semiconductor substrate; and b) impinging laser energy upon the CVD metal layer at an optical fluence of from 0.05 Joules/cm.sup.2 to 0.30 Joules/cm.sup.2 for a period of time sufficient to relieve mechanical stress associated with the CVD metal layer yet insufficient to melt the CVD metal layer. In accordance with another aspect of the invention, such treatment method could also be used to form a desired silicide layer in the same step.Type: GrantFiled: January 25, 1991Date of Patent: March 10, 1992Assignee: Micron Technology, Inc.Inventors: Chang Yu, Trung T. Doan, Gurtej S. Sandhu
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Patent number: 5073518Abstract: A method of forming a conductive via plug or an interconnect line, or both, of solid ductile metal within an integrated circuit using plastic deformation of the solid metal, and a dry polishing method of removing excess metal from a metal layer atop an underlying layer on a semiconductor substrate wafer. The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. If both conductive via plugs and interconnect lines are both required within the circuit, a first masking step defines the interconnect lines. A first etch creates channels in the interconnect line locations. A second masking step defines the vias. A second etch creates the vias which pass through the dielectric layer to conductive regions below where contact is to be made. A layer of solid ductile metal is then deposited on top of the dielectric layer.Type: GrantFiled: June 20, 1991Date of Patent: December 17, 1991Assignee: Micron Technology, Inc.Inventors: Trung Doan, Mark E. Tuttle, Tyler A. Lowrey
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Patent number: 5069002Abstract: An apparatus for detecting a planar endpoint on a semiconductor wafer during mechanical planarization of the wafer. The planar endpoint is detected by sensing a change in friction between the wafer and a polishing surface. This change of friction may be produced when, for instance, an oxide coating of the wafer is removed and a harder material is contacted by the polishing surface. In a preferred form, the change in friction is detected by rotating the wafer and polishing surface with electric motors and measuring current changes on one or both of the motors. This current change can then be used to produce a signal to operate control means for adjusting or stopping the process.Type: GrantFiled: April 17, 1991Date of Patent: December 3, 1991Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Laurence D. Schultz, Trung T. Doan