Abstract: The present invention develops a bond pad interconnect in an integrated circuit device, by forming an aluminum pad; bonding a metal layer (such as copper (Cu), nickel (Ni), tungsten (W), gold (Au), silver (Ag) or platinum (Pt)) or a metal alloy (such as titanium nitride) to the aluminum bond pad by chemical vapor deposition or by electroless deposition; and adhering a conductive epoxy film to the metal layer, thereby forming a low resistive bond pad interconnect.

Abstract: A process for forming an electrical connection in a semiconductor device between an aluminum interconnect and the substrate avoids junction spiking at temperatures (1000.degree. C.-1500.degree. C.) significantly above the standard semiconductor device fabrication temperatures (<500.degree. C.). An insulating layer is formed over an upper surface of the substrate with a via formed through the insulating layer to expose a portion of the substrate to which electrical connection is to be made. A first refractory metal barrier layer is formed over the insulating layer and the exposed portion of the substrate. Preferably, the first barrier layer is TiN.

Abstract: Disclosed is a chemical vapor deposition (CVD) method of providing a conformal layer of titanium silicide atop a semiconductor wafer within a chemical vapor deposition reactor. Such includes, a) positioning a wafer within the CVD reactor; b) injecting selected quantities of a gaseous titanium halide, or alternately or in addition thereto a gaseous titanium organometallic precursor, a gaseous compound of the formula Si.sub.n H.sub.2n+2 where "n" is an integer greater than or equal to 2, and a carrier gas to within the reactor; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the titanium halide and Si.sub.n H.sub.2n+2 to deposit a film on the wafer, the film comprising a titanium silicide, the method being void of use of high intensity light during processing.

Abstract: A method for reducing the effects of buckling, cracking, or wrinkling in multilayer heterostructures is provided. The method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer by exposing the substrate to a gas and radiant energy. A second layer is formed superjacent the barrier film. The substrate is heated to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step. Further, it enables the planarization layer to go through a solid state reaction and the second layer to obtain a uniform reflow.

Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

Abstract: An improved internal line up clamp (10) is disclosed which has an integral back up ring (12). A first set of pipe clamps (22) move radially outward to engage the inner surface of a first pipe (14). A second set of pipe clamps (62) and a set of back up ring segments (88) are simultaneously moved radially outward into engagement with the inner surface of the pipes. The back up ring segments (88) are spring loaded to exert a relatively constant back up force against the inner surface of the pipes at the weld. In a modification, a fill block (118) can be used to fill the gap between adjacent back up ring segments when engaging the inner surface of the pipe.

Abstract: A semiconductor processing method of chemical mechanical polishing a predominately copper containing metal layer on a semiconductor substrate includes, a) providing a chemical mechanical polishing slurry comprising H.sub.2 0, a solid abrasive material, and a third component selected from the group consisting of HNO.sub.3, H.sub.2 SO.sub.4, and AgNO.sub.3 or mixtures thereof; and b) chemical mechanical polishing a predominately copper containing metal layer on a semiconductor substrate with the slurry. Such slurry also constitutes part of the invention. Such slurry may also contain an additional oxidant selected from the group consisting of H.sub.2 0.sub.2, HOCl, KOCl, KMnO.sub.4 and CH.sub.3 COOH or mixtures thereof to form a copper oxide passivating-type layer at the copper surface.

Abstract: A process to create a faceted (prograde) profile for an integrated circuit, in which the top corners of a layer disposed over a feature are preferentially etched, thereby creating slopes. The profile which results from the deposit of subsequent layers is more easily etched as a result of the contour imparted by the faceted edges. Since the subsequent layers are placed in the "line of sight" of the etch plasma, there are significantly fewer "stringers.

Abstract: The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

Abstract: In semiconductor manufacture, a pulse plasma enhanced chemical vapor deposition (PPECVD) method is provided for depositing a conductive film of low resistivity on a substrate. The PPECVD method is especially suited to the deposition of metal silicides such as TiSi.sub.x on a silicon substrate during contact metallization. The PPECVD method can be carried out in a vacuum reaction chamber of a cold wall CVD reactor. A metal precursor deposition gas such as TiCl.sub.4 is reacted with a silicon source gas such as SiH.sub.4 at a deposition temperature of about 500.degree. C. For generating a pulsed plasma, an rf power supply is coupled to the reaction chamber and to a pulse generator.

Abstract: A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.

Abstract: A transceiver has a transmitter portion using active comparators coupled to single low level positive bias source to enable low powered drain transmit and receive conversion of TTL input signals to LLS (low level serial) data output signals for a coaxial data transmission cable. The transceiver also provides a constant impedance for a coaxial or triaxial transmission cable during active transmission periods, standby periods and power-off periods to provide a cost effective method to transmit and receive data.

Abstract: A prefabricated collapsible formwork module is assembled at a factory site, including the provision of a pair of sheathing panels which can be made of insulating material, as well as the mounting of the vapor barrier, the filler strips, bearing blocks, and flexible or collapsible connecting elements extending between the panels extending between the panels to retain the panels when they are being erected. The sheathing panels may also have a waterproof membrane applied thereto, and the concrete reinforcement is assembled between the sheathing panels at the factory site. When the formwork module is fully assembled, it is then collapsed, that is, by moving one sheathing panel against the other including collapsing the collapsible connecting elements and sandwiching the concrete reinforcement which is preferably in the form of a grid, and the formwork module can then be stored and transported to a building site.

Abstract: A method of providing a silicon film having a roughened outer surface atop a semiconductor wafer comprises: a) placing a semiconductor wafer into a plasma enhanced RF powered chemical vapor deposition reactor; and b) plasma enhanced chemical vapor depositing a layer of silicon over the wafer surface by providing quantities of a silicon source gas, a carrier gas, and TiCl.sub.4 to the reactor, the atomic ratio of the quantities of silicon source gas and TiCl.sub.4 being greater than or equal to 4 at the wafer surface; and by maintaining the reactor at a selected RF power, pressure and temperature; the RF power being supplied at a frequency of at least 5 MHz and preferably at least 10 MHz, the quantities of silicon source gas, RF power, temperature and pressure being effective to produce a predominately silicon film having an outer surface, the quantity of TiCl.sub.

Abstract: Chemical-mechanical polishing methods are disclosed for removing insulating inorganic metal oxide materials from semiconductor wafers. Such utilize aqueous acids or base slurries having a pK ionization constant of less than or equal to 5.0. Alternately, aqueous slurries having an oxidizing agent with an E.degree. reduction potential of greater than or equal to 1.0 volt are utilized. Further alternatively, non-aqueous slurries having a liquid halogenated or pseudohalogenated reactant are utilized. Further, slurries having an organic ligand precursor are utilized.

Abstract: A semiconductor wafer has a surface layer to be planarized in a chemical mechanical polishing (CMP) process. An area of the layer that is higher than another area is altered so that the removal rate is higher. For example, if the surface layer is TEOS oxide, the higher layer may be bombarded with boron and phosphorus to produce BPSG, which has a polishing rate 2-3 times that of the TEOS. Upon CMP planarization, the higher area erodes faster resulting in improved planarization. Alternatively, the lower area may be doped with nitrogen to produce a nitride which is more resistant to CMP, with the same result. Likewise areas, such as tungsten troughs, which tend to be dished by CMP, may be changed to WNx which is more resistant to the tungsten CMP than the adjacent tungsten, eliminating the dishing upon planarization.

Abstract: A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regi

Abstract: The present invention relates to a process of making a concentrate of coagulation proteins starting with whole human or animal plasma. This concentrate is used as a biological adhesive when extemporaneously mixed to thrombin. The concentrated proteins include mostly fibrinogen, fibrin stabilizing factor (factor XIII) and fibronectin. The claimed process has the advantage of being short of execution while providing an excellent yield of coagulable proteins. No protease inhibitor has to be added during the process. The process involves steps of acidic precipitation in presence of amino-6 hexanoic acid which prevents co-precipitation of plasminogen with the desired coagulable proteins. The proteins so obtained are very stable after reconstitution in water for at least 24 hours at room or body temperature. After mixing with thrombin, the adhesive shows excellent strength and biocompatibility.

Abstract: A method of providing a conformal layer of TiSi.sub.x atop a semiconductor wafer within a chemical vapor deposition reactor includes the following steps: a) positioning a wafer within the reactor; b) injecting selected quantities of gaseous Ti(NR.sub.2).sub.4 precursor, gaseous silane and a carrier gas to within the reactor, where R is selected from the group consisting of H and a carbon containing radical, the quantities of Ti(NR.sub.2).sub.4 precursor and silane being provided in a volumetric ratio of Ti(NR.sub.2).sub.4 to silane of from 1:300 to 1:10, the quantity of carrier gas being from about 50 sccm to about 2000 sccm and comprising at least one noble gas; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the precursor and silane to deposit a film on the wafer, the film comprising a mixture of TiSi.sub.x and TiN, the selected temperature being from about 100.degree. C. to about 500.degree. C.

Abstract: A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the islating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.