Patents by Inventor Tsung Yuan Chen

Tsung Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786304
    Abstract: A method for fabricating a near-field transducer (NFT) for a heat assisted magnetic recording (HAMR) write apparatus is described. The HAMR write apparatus is coupled with a laser for providing energy and has a media-facing surface (MFS) configured to reside in proximity to a media during use. The method includes providing a stack on an underlayer. The stack includes an endpoint detection layer, an optical layer and an etchable layer. The optical layer is between the etchable and endpoint detection layers. The etchable layer is patterned to form a mask. A portion of the optical layer is removed. A remaining portion of the optical layer has a bevel at a bevel angle from the MFS location. The bevel angle is nonzero and acute. The NFT is provided such that the NFT has an NFT front surface adjoining the bevel and at the bevel angle from the MFS location.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 10, 2017
    Assignee: WESTERN DIGITAL (FREMONT), LLC
    Inventors: Shawn M. Tanner, Mingjun Yu, Min Zheng, Kyung Lee, Tsung Yuan Chen
  • Patent number: 9536064
    Abstract: An operation method of an electronic apparatus is provided, wherein a setting procedure of safety mechanism is executed first. The procedure includes: receiving a setting operation through a setting interface so as to select plural sensing units from a sensing unit group; creating a unlocking information according to the setting operation, wherein the unlocking information includes an enabling sequence of the selected sensing units; making the unlocking information associated with the operation function. After finishing the setting procedure of safety mechanism, when a trigger event conforming to the unlocking information is received, the operation corresponding to the unlocking information is executed.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: January 3, 2017
    Assignee: Wistron Corporation
    Inventors: Yung-Yen Chang, Tsung-Yuan Chen
  • Patent number: 9510464
    Abstract: A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: November 29, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
  • Patent number: 9380706
    Abstract: A substrate strip with wiring is provided. The substrate strip includes a plurality of wiring blocks, a carrying substrate, and an adhesive layer. Each of the wiring blocks includes at least one wiring board unit, and each of the wiring board unit includes an insulating layer and a wiring layer disposed on the insulating layer. The carrying substrate has a carrying surface. The adhesive layer is disposed between the carrying surface and the wiring layers, and adheres to the wiring blocks and the carrying substrate. When the adhesive layer is separated from the wiring blocks, the wiring layers are kept on the insulating layers. Further, a manufacturing method for the substrate is provided.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 28, 2016
    Assignee: Unimicron Technology Corp.
    Inventor: Tsung-Yuan Chen
  • Patent number: 9324664
    Abstract: An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first surface, a second surface opposite to each other and a chip container passing through the first surface and the second surface. The chip is disposed in the chip container. The chip includes an active surface and a protrusion and a top surface of the protrusion is a part of the active surface. The first circuit layer is disposed on the first surface and electrically connected to the core layer and the chip. The first circuit layer has a through hole. The protrusion of the chip is situated within the through hole, and the top surface of the protrusion is exposed to receive an external signal. The second circuit layer is disposed on the second surface and electrically connected to the core layer.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 26, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Wei-Ming Cheng
  • Patent number: 9307651
    Abstract: A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 5, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang
  • Patent number: 9237643
    Abstract: A circuit board structure including a dielectric layer, a fine circuit pattern and a patterned conductive layer is provided, wherein the fine circuit pattern is embedded in a surface of the dielectric layer, and the patterned conductive layer is disposed on another surface of the dielectric layer and protrudes therefrom.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: January 12, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
  • Publication number: 20160007472
    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is foamed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen, Shih-Lian Cheng
  • Patent number: 9161454
    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: October 13, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen, Shih-Lian Cheng
  • Patent number: 9116191
    Abstract: A voltage-drop testing system, including a voltage-drop control apparatus, and a voltage-drop testing method adapted for the voltage-drop testing system based on LABVIEW department platform. When the LABVIEW department platform 12 is running, different groups of test data may be transferred to the PLD tester 20, when the PLD tester 20 finishes the testing based on all groups of test data, the PLD tester 20 feeds back the test results to the LABVIEW department platform 12, and the LABVIEW department platform 12 creates the voltage-drop testing graphic frame displaying the test results for the electronic device under test 2 for the convenience of a user.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: August 25, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Tsung-Yuan Chen, Kuei-Chih Hou, Wen-Kai Chiang
  • Patent number: 9084379
    Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 14, 2015
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Chun-Chien Chen, Cheng-Po Yu
  • Publication number: 20150153795
    Abstract: A portable device and a method for enabling the portable device are disclosed. The portable device comprises a power module, a processing module, a sensing module, and an enable control module. The power module is configured to provide electric power. The processing module is configured to run an operating system to drive the portable device when the processing module itself is enabled. The sensing module is configured to sense a gesture to generate a group of touch sensing signals, and to judge whether the group of touch sensing signals conform to a group of predefined signals so as to generate an operating system enabling signal. The enable control module is configured to temporarily enable the sensing module according to a switching signal, and to enable the processing module according to the operating system enabling signal.
    Type: Application
    Filed: April 23, 2014
    Publication date: June 4, 2015
    Applicant: Wistron Corp.
    Inventors: Tsung Yuan CHEN, Yung-Yen CHANG
  • Publication number: 20150113256
    Abstract: An operation method of an electronic apparatus is provided, wherein a setting procedure of safety mechanism is executed first. The procedure includes: receiving a setting operation through a setting interface so as to select plural sensing units from a sensing unit group; creating a locking information according to the setting operation, wherein the locking information includes an enabling sequence of the selected sensing units; making the locking information associated with the operation function. After finishing the setting procedure of safety mechanism, when a trigger event conforming to the locking information is received, the operation corresponding to the locking information is executed.
    Type: Application
    Filed: February 24, 2014
    Publication date: April 23, 2015
    Applicant: Wistron Corporation
    Inventors: Yung-Yen Chang, Tsung-Yuan Chen
  • Patent number: 8955218
    Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: February 17, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Shih-Lian Cheng
  • Publication number: 20150042554
    Abstract: A method for adjusting screen displaying mode and an electronic device suitable for the method are provided; the electronic device has a body sensor. The method includes: determining whether the body sensor has detected a body contact; when the body contact is detected by the body sensor, not adjusting a screen displaying mode of the electronic device; when the body contact is not detected by the body sensor, determining whether to adjust the screen displaying mode of the electronic device according to a tilt status of the electronic device.
    Type: Application
    Filed: November 6, 2013
    Publication date: February 12, 2015
    Applicant: Wistron Corporation
    Inventors: Tsung-Yuan Chen, Yung-Yen Chang, Yen-Yu Lee
  • Patent number: 8943683
    Abstract: A fabricating method of an embedded package structure includes following steps. First and second boards are combined to form an integrated panel. First and second circuit structures are respectively formed on the first and second boards that are then separated. An embedded element is electrically disposed on the first circuit structure. First and second conductive bumps are respectively formed on a conductive circuit substrate and the second circuit structure. First and second semi-cured films are provided; a laminating process is performed to laminate the first circuit structure on the first board, the first and second semi-cured films, the conductive circuit substrate, and the second circuit structure on the second board. The first and second semi-cured films encapsulate the embedded element. The first and second conductive bumps respectively pierce through the first and second semi-cured films and are electrically connected to the first circuit structure and the conductive circuit substrate, respectively.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: February 3, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Ming-Huang Ting
  • Publication number: 20140239463
    Abstract: An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first surface, a second surface opposite to each other and a chip container passing through the first surface and the second surface. The chip is disposed in the chip container. The chip includes an active surface and a protrusion and a top surface of the protrusion is a part of the active surface. The first circuit layer is disposed on the first surface and electrically connected to the core layer and the chip. The first circuit layer has a through hole. The protrusion of the chip is situated within the through hole, and the top surface of the protrusion is exposed to receive an external signal. The second circuit layer is disposed on the second surface and electrically connected to the core layer.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Wei-Ming Cheng
  • Publication number: 20140174804
    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.
    Type: Application
    Filed: December 24, 2012
    Publication date: June 26, 2014
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen, Shih-Lian Cheng
  • Publication number: 20140175050
    Abstract: A method fabricates a magnetic transducer having an ABS location. Etch stop and nonmagnetic etchable layers are provided. A side shield layer is provided between the ABS location and the etch stop and etchable layers. Part of the side shield and etchable layers are removed using a first removal process. This portion of the pole trench formed has a top wider than the bottom in the side shield layer. Part of the etchable layer is removed using a second removal process, thereby forming the pole trench. The pole trench has a bottom and a top wider than the bottom in the side shield layer and substantially perpendicular sidewalls in the etchable layer. A nonmagnetic side gap layer is provided. A remaining portion of the pole trench has a location and profile for a pole. At least part of the pole is in the pole trench.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: WESTERN DIGITAL (FREMONT), LLC
    Inventors: JINQIU ZHANG, XIAOYU YANG, FENG LIU, MING JIANG, TSUNG YUAN CHEN
  • Patent number: 8735742
    Abstract: A cabinet includes a chassis and an electromagnetic interference (EMI) shielding apparatus. The shielding apparatus includes a bracket installed to a first end of the chassis, a shaft rotatably installed in the bracket, and a shielding member reeled about the shaft. The shielding member includes a first end fixed to the shaft, and a second end opposite to the first end and forming a holder. A second end of the chassis forms a latch opposite to the bracket for engaging with the holder. The shielding member is made of EMI shielding material, and the shielding member is wound on or let out from the shaft as the shaft rotates.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 27, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Tsung-Yuan Chen