Patents by Inventor Tsung Yuan Chen
Tsung Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8111479Abstract: A magnetic write head for perpendicular magnetic data recording having a trailing shield with a two step throat height. The trailing shield is formed over a non-magnetic bump that forms a notch in the leading edge of the trailing shield. This notch defines a first, smaller throat height closest to the write pole and a larger throat height away from the write pole. The smaller throat height near the write pole prevents excess magnetic flux from leaking to the write pole, thereby ensuring efficient strong write field. The larger trailing shield throat height away from the write pole prevents magnetic saturation of the trailing shield and also greatly facilitates manufacturing avoiding problems related to variations and deviations in manufacturing processes used to define the trailing shield.Type: GrantFiled: October 23, 2007Date of Patent: February 7, 2012Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Tsung Yuan Chen, Wen-Chien David Hsiao, Yimin Hsu, Vladimir Nikitin, Changqing Shi
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Publication number: 20110303442Abstract: A substrate strip with wiring is provided. The substrate strip includes a plurality of wiring blocks, a carrying substrate, and an adhesive layer. Each of the wiring blocks includes at least one wiring board unit, and each of the wiring board unit includes an insulating layer and a wiring layer disposed on the insulating layer. The carrying substrate has a carrying surface. The adhesive layer is disposed between the carrying surface and the wiring layers, and adheres to the wiring blocks and the carrying substrate. When the adhesive layer is separated from the wiring blocks, the wiring layers are kept on the insulating layers. Further, a manufacturing method for the substrate is provided.Type: ApplicationFiled: May 19, 2011Publication date: December 15, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: Tsung-Yuan CHEN
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Patent number: 8058561Abstract: A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed.Type: GrantFiled: August 18, 2008Date of Patent: November 15, 2011Assignee: Unimicron Technology Corp.Inventors: Chun-Chien Chen, Tsung-Yuan Chen
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Patent number: 8049114Abstract: A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.Type: GrantFiled: March 22, 2009Date of Patent: November 1, 2011Assignee: Unimicron Technology Corp.Inventors: Kuo-Ching Chen, Tsung-Yuan Chen, Cheng-Pin Chien
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Patent number: 8018678Abstract: A method for providing a perpendicular magnetic recording (PMR) head is disclosed. The method comprises: providing a stop layer; providing an insulating layer over the stop layer; forming a pole trench in the insulating layer by performing a reactive ion etching (RIE) process in the insulating layer over the stop layer; forming an electronic lapping guide (ELG) in the insulating layer by performing the RIE process in the insulating layer over the stop layer; and providing a PMR pole in which at least a portion of the PMR pole resides in the pole trench.Type: GrantFiled: November 26, 2008Date of Patent: September 13, 2011Assignee: Western Digital (Fremont), LLCInventors: Jinqiu Zhang, Tsung Yuan Chen, Steven C. Rudy
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Publication number: 20110155440Abstract: A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.Type: ApplicationFiled: May 20, 2010Publication date: June 30, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Publication number: 20110155428Abstract: A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer.Type: ApplicationFiled: May 24, 2010Publication date: June 30, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Publication number: 20110155441Abstract: A process for fabricating a circuit board is provided. A circuit substrate having a first surface and a first circuit layer is provided. A first dielectric layer having a second surface is formed on the circuit substrate and covers the first surface and the first circuit layer. An antagonistic activation layer is formed on the second surface. The antagonistic activation layer is irradiated by a laser beam to form at least a blind via extended from the antagonistic activation layer to the first circuit layer and an intaglio pattern. A first conductive layer is formed inside the blind via. A second conductive layer is formed in the intaglio pattern and the blind via. The second conductive layer covers the first conductive layer and is electrically connected with the first circuit layer through the first conductive layer. The antagonistic activation layer is removed to expose the second surface.Type: ApplicationFiled: May 20, 2010Publication date: June 30, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Publication number: 20110147339Abstract: A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.Type: ApplicationFiled: June 3, 2010Publication date: June 23, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Shu-Sheng Chiang, Tsung-Yuan Chen, Wei-Ming Cheng
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Publication number: 20110147056Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.Type: ApplicationFiled: May 28, 2010Publication date: June 23, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Publication number: 20110147342Abstract: A method for fabricating a wiring structure of a wiring board is provided. First, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, an intaglio pattern exposing the insulation layer is formed on an outer surface of the film. The intaglio pattern is formed by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern. The activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the film and the activated layer on the outer surface are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by chemical deposition method.Type: ApplicationFiled: June 14, 2010Publication date: June 23, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Shu-Sheng Chiang, Tsung-Yuan Chen, Wei-Ming Cheng
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Publication number: 20110114373Abstract: A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.Type: ApplicationFiled: March 26, 2010Publication date: May 19, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Patent number: 7931818Abstract: A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure.Type: GrantFiled: November 2, 2007Date of Patent: April 26, 2011Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Chun-Chien Chen
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Patent number: 7926172Abstract: An embedded circuit board including a glass fiber layer, two dielectric layers, and two circuit layers is provided. The glass fiber layer has a first surface and a second surface corresponding to the first surface. The dielectric layers are disposed on the first surface and the second surface, respectively. The circuit layers are embedded in the dielectric layers above the first surface and the second surface, respectively. The outer surface of each circuit layer is coplanar with the outer surface of each dielectric layer, and a distance between the circuit layer and the glass fiber layer is greater than or equal to 3 ?m. In addition, a process of the embedded circuit board is provided.Type: GrantFiled: July 9, 2007Date of Patent: April 19, 2011Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang
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Publication number: 20110063222Abstract: A method in a KVM switch system for interacting with the user to switch computer ports using a touch panel device having a touch-sensitive screen is described. The system allows a user to accomplish port switching by “drawing” a symbol (such as an Arabic number) representing a port number on the touch screen, coupled with other actions, such as one or more touches of the screen, an action using another input device such as a mouse, keyboard, buttons, etc., to confirm the port number input.Type: ApplicationFiled: September 17, 2009Publication date: March 17, 2011Applicant: ATEN INTERNATIONAL CO., LTD.Inventors: Hung Chi CHU, Tsung Yuan CHEN
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Publication number: 20100314352Abstract: A fabricating method of an embedded package structure includes following steps. First, a first circuit structure and a second circuit structure are formed respectively on a first board and a second board which are combined to form an integrated panel. The first board and the second board are then separated. Next, an embedded element is electrically disposed on the first circuit structure. At least one conductive bump is formed on the second circuit structure. Thereafter, a semi-cured film is provided, and a laminating process is performed to laminate the first circuit structure on the first board, the semi-cured film, and the second circuit structure on the second board. The semi-cured film encapsulates the embedded element and the at least one conductive bump pierces through the semi-cured film and electrically connects the first circuit structure.Type: ApplicationFiled: September 8, 2009Publication date: December 16, 2010Inventors: Tsung-Yuan Chen, Ming-Huang Ting
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Patent number: 7841068Abstract: A method of fabricating a single-pole perpendicular magnetic recording head to contain a bevel angle promotion layer that facilitates the fabrication of the bevel angle in a trapezoidal main pole. The bevel angle promotion layer is made of a non-magnetic material that is softer than the material (e.g., Al2O3) that normally underlies the main pole. In one embodiment, the bevel angle promotion layer is formed between an end of the yoke and the air bearing surface (ABS), with the top surface of the bevel angle promotion layer being substantially coplanar with the top surface of the yoke. In other embodiment the bevel angle promotion layer is integrated with a leading edge taper material, which is formed of a magnetic material, to broaden the magnetic flux path between the yoke and the main pole.Type: GrantFiled: July 2, 2007Date of Patent: November 30, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Tsung Yuan Chen, Yimin Hsu, Yinshi Liu
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Patent number: 7804662Abstract: In a perpendicular recording head, a notch is formed in the top write gap at a location on top of the main pole. A perpendicular head with this notched top write gap structure has less transition curvature and better writability while reducing the adjacent track interference (ATI). Also, the process used to fabricate the head ensures that the trailing edge (writing edge) of the main pole is extremely flat with no corner rounding.Type: GrantFiled: December 26, 2006Date of Patent: September 28, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Tsung Yuan Chen, Hung-Chin Guthrie, Yimin Hsu, Ming Jiang
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Publication number: 20100236817Abstract: A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.Type: ApplicationFiled: March 22, 2009Publication date: September 23, 2010Inventors: Kuo-Ching Chen, Tsung-Yuan Chen, Cheng-Pin Chien
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Publication number: 20100206619Abstract: A package substrate structure includes a substrate with a first side and a second side opposite to the first side, a via connecting the first side and the second side, a cavity in the substrate and on the first side, and a patterned conductive layer disposed on at least one of the first side and the second side, filling the cavity and the via, and including a first conductive layer, a second conductive layer and a third conductive layer. The second conductive layer is different from at least one of the first conductive layer and the third conductive layer.Type: ApplicationFiled: June 16, 2009Publication date: August 19, 2010Inventors: Kuo-Ching Chen, Tsung-Yuan Chen, Cheng-Pin Chien