Patents by Inventor Tsung Yuan Chen

Tsung Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7804662
    Abstract: In a perpendicular recording head, a notch is formed in the top write gap at a location on top of the main pole. A perpendicular head with this notched top write gap structure has less transition curvature and better writability while reducing the adjacent track interference (ATI). Also, the process used to fabricate the head ensures that the trailing edge (writing edge) of the main pole is extremely flat with no corner rounding.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: September 28, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tsung Yuan Chen, Hung-Chin Guthrie, Yimin Hsu, Ming Jiang
  • Publication number: 20100236817
    Abstract: A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.
    Type: Application
    Filed: March 22, 2009
    Publication date: September 23, 2010
    Inventors: Kuo-Ching Chen, Tsung-Yuan Chen, Cheng-Pin Chien
  • Publication number: 20100206619
    Abstract: A package substrate structure includes a substrate with a first side and a second side opposite to the first side, a via connecting the first side and the second side, a cavity in the substrate and on the first side, and a patterned conductive layer disposed on at least one of the first side and the second side, filling the cavity and the via, and including a first conductive layer, a second conductive layer and a third conductive layer. The second conductive layer is different from at least one of the first conductive layer and the third conductive layer.
    Type: Application
    Filed: June 16, 2009
    Publication date: August 19, 2010
    Inventors: Kuo-Ching Chen, Tsung-Yuan Chen, Cheng-Pin Chien
  • Patent number: 7774932
    Abstract: A circuit board process is provided. First, multiple carriers is provided, and a first conductive layer having multiple concave structures is formed on each carrier. A dielectric layer is then provided, and the carriers with the first conductive layers are laminated on a first and a second surface of the dielectric layer respectively, wherein portions of the first conductive layers are embedded in the first and second surfaces. Next, the carriers are removed. Thereafter, the first conductive layer corresponding to at least one concave is removed to expose a portion of the dielectric layer. Next, the exposed dielectric layer is removed to form an opening. A second conductive layer is then formed on the inner wall of the opening, wherein the second conductive layer is electrically connected to the first conductive layers on both sides of the dielectric layer.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: August 17, 2010
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Chien Chen, Tsung-Yuan Chen
  • Publication number: 20100200154
    Abstract: A process for fabricating a circuit board with an embedded passive component is provided. An electrode-patterned layer having electrodes is formed on a surface of a conductive layer. A passive component material is filled in the intervals between the electrodes. The conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. The conductive layer is patterned to form a circuit layer.
    Type: Application
    Filed: April 19, 2010
    Publication date: August 12, 2010
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventor: Tsung-Yuan Chen
  • Patent number: 7742258
    Abstract: A method for fabricating a magnetic head with a trapezoidal shaped pole piece tip is described. The body of the main pole piece is deposited; then one or more layers for the pole piece tip are deposited. A bed material is deposited over the pole piece tip material. A void is formed in the bed material over the area for the pole piece tip. The void is filled with an ion-milling resistant material such as alumina preferably using atomic layer deposition or atomic layer chemical vapor deposition. The excess ion-milling resistant material and the bed material are removed. The result is an ion-milling mask formed over the area for the pole piece tip. Ion milling is then used to remove the unmasked material in the pole piece tip layer and to form a beveled pole piece tip and preferably a beveled face on the main pole piece.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: June 22, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tsung Yuan Chen, David Patrick Druist, Quang Le, Kim Y. Lee, Chun-Ming Wang, Howard Gordon Zolla
  • Patent number: 7733662
    Abstract: A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 8, 2010
    Assignee: Unimicron Technology Corp.
    Inventor: Tsung-Yuan Chen
  • Publication number: 20100112486
    Abstract: A method and system for providing a PMR pole in a magnetic recording transducer including an intermediate layer are disclosed. The method and system include providing a mask on the intermediate layer. The mask includes a line having at least one side. A hard mask layer is provided on the mask. At least a portion of the hard mask layer resides on the side(s) of the line. At least part of the hard mask layer on the side(s) of the line is removed. Thus, at least a portion of the line is exposed. The line is then removed, providing an aperture in the hard mask corresponding to the line. The method also includes forming a trench in the intermediate layer under the aperture. The trench top is wider than its bottom. The method further includes providing a PMR pole, at least a portion of which resides in the trench.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 6, 2010
    Applicant: WESTERN DIGITAL (FREMONT), LLC
    Inventors: JINQIU ZHANG, HAI SUN, HONGPING YUAN, TSUNG YUAN CHEN, GUANXIONG LI
  • Publication number: 20100065324
    Abstract: An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 18, 2010
    Inventors: Yi-Chun Liu, Wei-Ming Cheng, Tsung-Yuan Chen, Shu-Sheng Chiang
  • Publication number: 20100065319
    Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
    Type: Application
    Filed: December 4, 2008
    Publication date: March 18, 2010
    Applicant: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Chun-Chien Chen, Cheng-Po Yu
  • Publication number: 20100044082
    Abstract: A wiring board including two wiring layers and a flexible core layer is provided. The flexible core layer is disposed between the wiring layers, and the flexible core layer is an insulator. A flexure of the wiring board is between 0 degree and 170 degrees.
    Type: Application
    Filed: October 29, 2008
    Publication date: February 25, 2010
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun-Chien Chen, Tsung-Yuan Chen, Cheng-Po Yu
  • Publication number: 20100038124
    Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Inventors: Yi-Chun Liu, Wei-Ming Cheng, Tsung-Yuan Chen, Shu-Sheng Chiang
  • Publication number: 20090284935
    Abstract: A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density.
    Type: Application
    Filed: December 29, 2008
    Publication date: November 19, 2009
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
  • Publication number: 20090282674
    Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.
    Type: Application
    Filed: December 29, 2008
    Publication date: November 19, 2009
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
  • Publication number: 20090273907
    Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, an active circuit, and two shielding circuits. The dielectric layer has an active surface. The active circuit is disposed on the active surface, and the shielding circuits are respectively disposed on two sides of the active circuit. The height of the shielding circuits is larger than the height of the active circuit.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Tzyy-Jang Tseng, Shu-Sheng Chiang, David C. H. Cheng
  • Publication number: 20090205852
    Abstract: A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed.
    Type: Application
    Filed: August 18, 2008
    Publication date: August 20, 2009
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun-Chien Chen, Tsung-Yuan Chen
  • Publication number: 20090166059
    Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit.
    Type: Application
    Filed: March 14, 2008
    Publication date: July 2, 2009
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tsung-Yuan Chen, Tzyy-Jang Tseng, Shu-Sheng Chiang, David C. H. Cheng
  • Patent number: 7536778
    Abstract: A method of fabrication is disclosed for a slider having sites for fabrication of a continuous coil having a set of front coils and a set of back coils and a center tab, where the slider includes underpass leads.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: May 26, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Amanda Baer, Tsung Yuan Chen, David Patrick Druist, Edward Hin Pong Lee
  • Publication number: 20090103211
    Abstract: A magnetic write head for perpendicular magnetic data recording having a trailing shield with a two step throat height. The trailing shield is formed over a non-magnetic bump that forms a notch in the leading edge of the trailing shield. This notch defines a first, smaller throat height closest to the write pole and a larger throat height away from the write pole. The smaller throat height near the write pole prevents excess magnetic flux from leaking to the write pole, thereby ensuring efficient strong write field. The larger trailing shield throat height away from the write pole prevents magnetic saturation oft the trailing shield and also greatly facilitates manufacturing avoiding problems related to variations and deviations in manufacturing processes used to define the trailing shield.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 23, 2009
    Inventors: Tsung Yuan Chen, Wen-Chien David Hsiao, Yimin Hsu, Vladimir Nikitin, Changqing Shi
  • Patent number: 7500303
    Abstract: A read head for a disk drive and a method of fabricating the read head with overlaid lead pads that contact the top surface of the sensor between the hardbias structures to define the electrically active region of the sensor are described. The invention deposits the GMR and lead layers before milling away the unwanted material. A photoresist mask with a hole defining the active area of the sensor is preferably patterned over a layer of DLC that is formed into a mask. A selected portion of the exposed lead material is then removed using the DLC as a mask defining the active region of the sensor. A photoresist mask pad is patterned to define the full sensor width. The excess sensor and lead material exposed around the mask is milled away. The layers for the hardbias structure are deposited.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 10, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tsung Yuan Chen, Kuok San Ho, Mustafa Michael Pinarbasi