Patents by Inventor Tung Chang

Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160293720
    Abstract: A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung CHANG, Sameer HADDAD, James Pak
  • Patent number: 9430605
    Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lai, Ming-Che Ho, Tzong-Hann Yang, Chien Rhone Wang, Chia-Tung Chang, Hung-Jui Kuo, Chung-Shi Liu
  • Publication number: 20160248423
    Abstract: A feedthrough signal transmission apparatus, fabricated on a single silicon, includes a plurality of feedthrough signal transmission circuits and a permanently on control cell that is coupled to the feedthrough signal transmission circuits, where each feedthrough signal transmission circuit of the feedthrough signal transmission circuits may include at least one sub-circuit that is kept in a power on state when the sub-circuit performs feedthrough signal transmission. For example, and the sub-circuit may include a permanently on-for-feedthrough repeater (e.g. a repeater that is kept in the power on state when the repeater performs feedthrough signal transmission). In addition, the permanently on control cell may be configured to maintain the power on state of the sub-circuit when the sub-circuit performs feedthrough signal transmission. For example, sub-circuits of the feedthrough signal transmission circuits are located at grid-based locations, respectively.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Inventors: Chien-Pang Lu, Yu-Tung Chang
  • Patent number: 9425612
    Abstract: An output power protection apparatus includes a DC conversion unit, an output protection unit, a high-voltage battery, a low-voltage battery, and a control unit. The DC conversion unit converts an input DC power into an output DC power. The output protection unit is connected in series to the DC conversion unit, and the output protection unit has a plurality of protection circuits connected in parallel to each other. When a short-circuit condition occurs between the high-voltage battery and the low-voltage battery or the low-voltage battery is reversely connected in polarity, the control unit generates a control signal to control the protection circuits to disconnect the connection between the low-voltage battery and a low-voltage device, and the DC conversion unit.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: August 23, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wen-Sheng Tsao, Chin-Hou Chen, Jui-Teng Chan, Chen-Tung Chang, Chen-Bin Huang, Wei-Cheng Peng
  • Publication number: 20160218113
    Abstract: Semiconductor devices and methods of manufacturing thereof are described. According to an example embodiment, a semiconductor device comprises: a substrate comprising a core region and a peripheral region, where the core region is adjacent to the peripheral region; a memory array comprising non-volatile memory cells that are located in the core region of the substrate; a high-voltage control logic comprising high-voltage transistors that are located in the peripheral region of the substrate; and a low-voltage control logic comprising low-voltage transistors that are located in the peripheral region of the substrate.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Inventors: Kuo Tung CHANG, Chun Chen, Shenqing Fang
  • Patent number: 9401433
    Abstract: A p-type metal oxide semiconductor material is provided, which is composed of AlxGe(1-x)Oy, wherein 0<x?0.6, and 1.0?y?2.0. The p-type metal oxide semiconductor material can be applied in a transistor. The transistor may include a gate electrode, a channel layer separated from the gate electrode by a gate insulation layer, and a source electrode and a drain electrode contacting two sides of the channel layer, wherein the channel layer is the p-type metal oxide semiconductor material.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 26, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shan-Haw Chiou, Tzu-Chi Chou, Wen-Hsuan Chao, Hsin-Ming Cheng, Mu-Tung Chang, Tien-Heng Huang, Ren-Fong Cai
  • Publication number: 20160187121
    Abstract: A non-destructive and optical measurement automation system for web thickness of microdrills and method thereof can obtain the measuring data corresponding to a certain section to be measured of a microdrill by means of automated optical measurement. Specifically speaking, the said system and method measure the section to be measured via an optical measuring plane formed by a measuring light beam, and the included angle between the optical measuring plane and the central axis of the microdrill is practically consistent with the helix angle of the microdrill. The said system and method then analyze the measuring data via a computer device to obtain the outer diameter and the depths of helical flutes corresponding to the section to be measured. Finally, the said system and method calculate the web thickness of the said section to be measured according to the outer diameter and the depths of helical flutes.
    Type: Application
    Filed: October 6, 2015
    Publication date: June 30, 2016
    Inventors: Wen-Tung CHANG, Jian-Hong WU
  • Patent number: 9368606
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 14, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Patent number: 9368588
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 14, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Kuo Tung Chang, Chun Chen, Shenqing Fang
  • Publication number: 20160131977
    Abstract: A method for fabricating a peripheral wiring unit of a touch panel includes the following steps: (a) forming a transparent conductive layer on a substrate, the substrate including a peripheral region and a window region surrounded by the peripheral region, and forming a photosensitive conductive layer on the peripheral region of the substrate, such that the photosensitive conductive layer at least partially overlies the transparent conductive layer; (b) exposing the photosensitive conductive layer by using a photomask; and (c) developing the exposed photosensitive conductive layer to form a peripheral wiring unit on the peripheral region of the substrate.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Inventors: Chao-Wen LEE, Hung-Sheng CHO, Tung-Chang TSAI
  • Publication number: 20160126250
    Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 5, 2016
    Applicant: Spansion LLC
    Inventors: Kuo Tung CHANG, Shenqing Fang, Timothy Thurgate
  • Publication number: 20160111292
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 21, 2016
    Applicant: Cypress Semiconductor Corporation
    Inventors: Mark RAMSBEY, Chun CHEN, Sameer HADDAD, Kuo Tung CHANG, Unsoon KIM, Shenqing FANG, Yu SUN, Calvin GABRIEL
  • Patent number: 9296086
    Abstract: An improved destructive and visual measurement automation system and a method for measuring a web thickness of a microdrill are provided. When a dual-axis motion platform module moves the microdrill to a first position, a reflection module reflects a first image in a first direction toward a second direction. A vision module receives the reflected first image in the second direction and outputs the received first image to a computer. According to the first image, the computer performs a positioning procedure and a grinding procedure to drive a drill grinding module to grind the microdrill to a sectional position to be measured of the microdrill. When the microdrill is moved to a second position, the vision module outputs a second image to the computer. According to the second image, the computer performs an image computing procedure to obtain the web thickness at the sectional position to be measured.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 29, 2016
    Assignee: National Taiwan Ocean University
    Inventors: Wen-Tung Chang, Yu-Yun Lu
  • Publication number: 20160075358
    Abstract: A collapsible trolley includes a frame, a carrier plate, two wheel units, a primary grip and two auxiliary grip units. The frame includes two lower tubes and two upper tubes each pivotally connected to a corresponding one of the lower tubes. The carrier plate is connected to the lower tubes. Each of the wheel units is connected to a corresponding one of the lower tubes. The primary grip is supported on the upper tubes. Each of the auxiliary grip units is pivotally connected to a corresponding one of the upper tubes.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Howard Simon, Wen Tung Chang
  • Patent number: 9276007
    Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 1, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
  • Publication number: 20160041659
    Abstract: A touch panel is provided. The touch panel includes a plurality of first electrodes disposed on a substrate. The first electrodes are parallel to each other and extend along a first direction. A conductive photoresist film including a plurality of second electrodes and an insulating photo-sensitive material layer is disposed on the first electrodes. The second electrodes are parallel to each other and extend along a second direction perpendicular to the first direction. The insulating photo-sensitive material layer is disposed between the first and second electrodes. Furthermore, a fabrication method of a touch panel is also provided. The method includes using a conductive photoresist film to form the touch panel.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 11, 2016
    Inventors: Huang-Cho CHEN, Tung-Chang TSAI, Hung-Sheng CHO
  • Patent number: 9245895
    Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: January 26, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
  • Publication number: 20160020199
    Abstract: A semiconductor structure includes a first spare cell region, a first conductive line and a second conductive line. The first spare cell region has a plurality of spare cells. The first conductive line is coupled between a first reference voltage and the plurality of spare cells, and is arranged for providing the first reference voltage to the plurality of spare cells of the first spare cell region. The second conductive line is coupled to a plurality of spare cells, and is arranged for providing a second reference voltage to the plurality of spare cells of the first spare cell region.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 21, 2016
    Inventors: Chih-Hsin Fu, Yu-Tung Chang
  • Publication number: 20150360122
    Abstract: An acoustic energy inductive device includes a first fabric, a second fabric, and a microphone. The second fabric and the first fabric are combined such that a resonant chamber is formed between the first fabric and the second fabric. The microphone is disposed in the resonant chamber for converting a sonic signal in the resonant chamber into an electrical signal. The first fabric and the second fabric are made of impermeable material.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 17, 2015
    Inventors: Yi-Yuan Chen, Cheng-Tung Chang, Chien-Lung Shen
  • Patent number: D755111
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: May 3, 2016
    Assignee: KENDA RUBBER IND. CO., LTD.
    Inventors: Ying-Ming Yang, Jih-Tung Chang