Patents by Inventor Tung Chang

Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Charge trapping split gate device and method of fabricating same
    Patent number: 9966477
    Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: May 8, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad
  • NAT traversal method, computer-readable medium, and system for mediating connection
    Patent number: 9942195
    Abstract: Disclosed herein is a network address translation (NAT) traversal method. A node sends a first, second, and third detection message from a local port to a first, second, and third response server, respectively, in order to receive from the response servers a first, second, and third response message, which respectively include a first, second, and third proximal external port number (EPN). The node then deduces a rule for proximal EPNs based on the received ones. Also disclosed is a system for mediating connection. The system assists a first node on a network in NAT traversal and includes at least three response servers, which receive detection messages from the first node and send back response messages that include EPNs.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: April 10, 2018
    Assignee: VIVOTEK INC.
    Inventors: Chia-Ming Kuo, Wei-Tung Chang
  • Charge trapping split gate embedded flash memory and associated methods
    Patent number: 9922833
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 20, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Ramsbey, Chun Chen, Sameer Haddad, Kuo Tung Chang, Unsoon Kim, Shenqing Fang, Yu Sun, Calvin Gabriel
  • Memory first process flow and device
    Patent number: 9917166
    Abstract: A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 13, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Suppression of program disturb with bit line and select gate voltage regulation
    Patent number: 9881683
    Abstract: Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: January 30, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Split-gate flash cell formed on recessed substrate
    Patent number: 9853039
    Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 26, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Split-gate flash cell formed on recessed substrate
    Patent number: 9818755
    Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Circuit layouts, methods and apparatus for arranging integrated circuits
    Patent number: 9805155
    Abstract: A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 31, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chien-Pang Lu, Yu-Tung Chang
  • TOUCH PANELS AND TOUCH DISPLAY DEVICES
    Publication number: 20170277314
    Abstract: A touch panel is provided. The touch panel includes a substrate having a touch area and a peripheral area adjacent to the touch area. A transparent conductive layer is disposed on the substrate, the transparent conductive layer includes a touch-sensing portion and a wiring portion, wherein the touch-sensing portion is electrically connected to the wiring portion, and wherein the touch-sensing portion is disposed corresponding to the touch area and the wiring portion is disposed corresponding to the peripheral area. A metal layer is disposed on the wiring portion of the transparent conductive layer and corresponding to the peripheral area. An insulating layer is disposed on the metal layer and corresponding to the peripheral area. A touch display device including the touch panel is also provided.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 28, 2017
    Inventors: Wei-Chih CHEN, Tung-Chang TSAI, Hung-Sheng CHO
  • TISSUE BOX
    Publication number: 20170259987
    Abstract: A tissue box may include a box unit having a first draw-out opening, and a locating piece, which is partially attached to a surface of the box unit having the first draw-out opening, comprises a second draw-out opening which is located at a position misaligned with the first draw-out opening such that an overlapping portion formed between the first draw-out opening and the second draw-out opening is configured to clamp and limit a position of the following tissue when one tissue is pulled out of the box unit.
    Type: Application
    Filed: December 29, 2016
    Publication date: September 14, 2017
    Applicants: Zhu-Jiang Construction Co., Ltd.
    Inventor: Ching-Tung Chang
  • Non-destructive and optical measurement automation system for web thickness of microdrills and method thereof
    Patent number: 9677876
    Abstract: A non-destructive and optical measurement automation system for web thickness of microdrills and method thereof can obtain the measuring data corresponding to a certain section to be measured of a microdrill by means of automated optical measurement. Specifically speaking, the said system and method measure the section to be measured via an optical measuring plane formed by a measuring light beam, and the included angle between the optical measuring plane and the central axis of the microdrill is practically consistent with the helix angle of the microdrill. The said system and method then analyze the measuring data via a computer device to obtain the outer diameter and the depths of helical flutes corresponding to the section to be measured. Finally, the said system and method calculate the web thickness of the said section to be measured according to the outer diameter and the depths of helical flutes.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: June 13, 2017
    Assignee: National Taiwan Ocean University
    Inventors: Wen-Tung Chang, Jian-Hong Wu
  • Memory First Process Flow and Device
    Publication number: 20170141201
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Application
    Filed: September 29, 2016
    Publication date: May 18, 2017
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Media stream providing device and method for connecting thereto, media streaming system, and computer-readable medium
    Patent number: 9559942
    Abstract: Disclosed herein, among others, is a media streaming system, comprising a registrar server, a media stream providing device, and a media stream receiving device. The registrar server is configured to register a piece of connection information associated with the media stream providing device, the connection information comprising a local network location, a public network location, a broker location, and a proxy location. The media stream receiving device is configured to obtain the connection information from the registrar server, and to commence measuring simultaneously, based on the aforementioned locations, first, second, third, and fourth costs for connecting to the media stream providing device via a local path, a remote path, a peer-to-peer path, and a proxy-assisted path, respectively. The media stream receiving device then selects one of those paths based on the measured costs.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 31, 2017
    Assignee: VIVOTEK, INC.
    Inventors: Chia-Ming Kuo, Wei-Tung Chang
  • Three-dimensional charge trapping NAND cell with discrete charge trapping film
    Patent number: 9508736
    Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
  • Feedthrough signal transmission circuit and method utilizing permanently on buffer and switchable normal buffer
    Patent number: 9484134
    Abstract: A feedthrough signal transmission circuit includes a first permanently on cell and a cell controlling unit. The first permanently on cell is arranged to transmit a first control signal. The cell controlling unit is coupled to the first permanently on cell, and includes a power switch and a plurality o buffers. The power switch is coupled to the first permanently on cell, arranged to receive a switch control signal and the first control signal, and selectively output the first control signal according to the switch control signal. The plurality of buffers is coupled to the power switch. Each of the buffers is arranged to buffer a data input only when powered by the first control signal output from the power switch.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 1, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chien-Pang Lu, Yu-Tung Chang
  • Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film
    Publication number: 20160307916
    Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 20, 2016
    Inventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
  • CIRCUIT LAYOUTS, METHODS AND APPARATUS FOR ARRANGING INTEGRATED CIRCUITS
    Publication number: 20160292340
    Abstract: A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.
    Type: Application
    Filed: January 28, 2016
    Publication date: October 6, 2016
    Inventors: Chien-Pang LU, Yu-Tung CHANG
  • Holder for dispenser element and candle
    Patent number: D771846
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 15, 2016
    Assignee: S. C. Johnson & Son, Inc.
    Inventors: Brian T. Davis, Shih-Tung Chang, Jacob S. Childs, Michel D. Arney
  • Vehicle tire
    Patent number: D780100
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: February 28, 2017
    Assignee: KENDA RUBBER IND. CO., LTD.
    Inventors: Ying-Ming Yang, Jih-Tung Chang
  • Holder for dispenser element and candle
    Patent number: D816872
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 1, 2018
    Assignee: S.C. Johnson & Son, Inc.
    Inventors: Brian T. Davis, Shih-Tung Chang, Jacob S. Childs, Michel D. Arney