Patents by Inventor Tung Chang

Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits with non-volatile memory and methods for manufacture
    Patent number: 8836006
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventors: Kuo Tung Chang, Chun Chen, Shenqing Fang
  • Process charging protection for split gate charge trapping flash
    Patent number: 8816438
    Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Sameer Haddad, Kuo Tung Chang, Mark Ramsbey, Unsoon Kim, Shenqing Fang
  • Integrated circuit with metal and semi-conducting gate
    Patent number: 8815727
    Abstract: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 26, 2014
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Angela T. Hui, Mark S. Chang, Kuo-Tung Chang, Scott A. Bell
  • System and method for improving reliability in a semiconductor device
    Patent number: 8802537
    Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: August 12, 2014
    Assignee: Spansion LLC
    Inventors: Yider Wu, Unsoon Kim, Kuo-Tung Chang, Harpreet Sachar
  • Adjusting sizes of connectors of package components
    Patent number: 8791579
    Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lai, Ming-Che Ho, Tzong-Hann Yang, Chien Rhone Wang, Chia-Tung Chang, Hung-Jui Kuo, Chung-Shi Liu
  • Memory system with Fin FET technology
    Patent number: 8785268
    Abstract: A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 22, 2014
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Lei Xue, Kuo-Tung Chang
  • THREE DIMENSIONAL CAPACITOR
    Publication number: 20140167220
    Abstract: Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Mark RAMSBEY, Unsoon KIM, Shenqing FANG, Chun CHEN, Kuo Tung CHANG
  • Integrated Circuits With Non-Volatile Memory and Methods for Manufacture
    Publication number: 20140167139
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Kuo Tung CHANG, Chun CHEN, Shenqing FANG
  • Process Charging Protection for Split Gate Charge Trapping Flash
    Publication number: 20140167135
    Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Sameer Haddad, Kuo Tung Chang, Mark Ramsbey, Unsoon Kim, Shenqing Fang
  • Memory First Process Flow and Device
    Publication number: 20140167140
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Chun CHEN, Unsoon KIM, Mark RAMSBEY, Kuo Tung CHANG, Sameer HADDAD, James PAK
  • Charge Trapping Split Gate Device and Method of Fabricating Same
    Publication number: 20140170843
    Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Shenqing FANG, Unsoon KIM, Mark RAMSBEY, Kuo Tung CHANG, Sameer HADDAD
  • Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
    Publication number: 20140167141
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Mark RAMSBEY, Chun CHEN, Sameer HADDAD, Kuo Tung CHANG, Unsoon KIM, Shenqing FANG, Yu SUN, Calvin GABRIEL
  • BIOLOGICAL DETECTING CHIP
    Publication number: 20140171343
    Abstract: A biological detecting chip comprising an optical fiber, at least one gas filter, an upper cap and a substrate is disclosed. The optical fiber has at least one detecting area disposed on an outer surface. The upper cap has at least two guiding channels passed through the upper cap, at least one discharge channel with two ends connecting to an upper portion of distinct guiding channels, an inlet and an outlet, wherein the gas filter is attached to an upside of the discharge channel to separate the discharge channel and an outside of the upper cap. The substrate has a test area and a plurality of directing channels, wherein the directing channel connects to the inlet and the guiding channel, connects to the guiding channel and the test area, and connects to the test area and the outlet.
    Type: Application
    Filed: January 18, 2013
    Publication date: June 19, 2014
    Applicant: ARDIC INSTRUMENTS CO.
    Inventors: YU CHENG SU, CHIA-YING LEE, CHIAO-TUNG CHANG, CHENG HAN CHEN
  • BIOMEDICAL MONITORING SYSTEM COMBINING A MOBILE DEVICE
    Publication number: 20140099237
    Abstract: The present invention provides a biomedical monitoring system combining a mobile device. Signals can be transmitted between the sensing device and the mobile device via the audio interface by modulating and demodulating the audio signals or encoding and decoding the digital signals. Thereby, it can be applied extensively to mobile devices having audio jacks and thus bringing more convenience. In addition, because the mobile devices inherently have the functions of operational processes, transmission, storage, interface operations, result displaying, network connection, image extraction, and power supply, the required components in sensing devices can be simplified substantially and hence reducing the volume and the manufacturing cost.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 10, 2014
    Applicant: ALCOR MICRO CORP.
    Inventors: Chi Tung CHANG, Shih Min LAN, Hao Yu CHENG
  • Memory Device with Charge Trap
    Publication number: 20140061771
    Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 6, 2014
    Applicants: Spansion, LLC., Advanced Micro Devices, Inc.
    Inventors: Meng Ding, Amol Ramesh Joshi, Lei Xue, Takashi Orimoto, Kuo-Tung Chang
  • ELECTRICAL CONNECTOR WITH PRINTED CIRCUIT BOARD
    Publication number: 20140057465
    Abstract: An electrical connector for a cable includes a PCB and a fixed element for holding the PCB. The PCB includes several first contacting fingers and second contacting fingers electrically connected to each other at different sides along a first direction. The first and second contacting fingers are respectively arranged along a second direction perpendicular to the first direction to be disposed in two rows. The second contacting fingers are connected to the cable. Wherein said PCB is longer than said fixed element so as to expose first contacting fingers at a front side of the fixed element along the first direction and form a mating port for a mating connector.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 27, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: SHIH-TUNG CHANG
  • Mechanisms for forming copper pillar bumps
    Patent number: 8659155
    Abstract: The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chih-Wei Lin, Ching-Wen Chen, Yi-Wen Wu, Chia-Tung Chang, Ming-Che Ho, Chung-Shi Liu
  • Etch stop layer for memory cell reliability improvement
    Patent number: 8658496
    Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 25, 2014
    Assignees: Advanced Mirco Devices, Inc., Spansion LLC
    Inventors: Hiroyuki Kinoshita, Angela Hui, Hsiao-Han Thio, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa
  • CONTACTS FOR SEMICONDUCTOR DEVICES
    Publication number: 20140042514
    Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicants: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Method for forming a semiconductor layer with improved gap filling properties
    Patent number: 8647969
    Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 11, 2014
    Assignee: Spansion LLC
    Inventors: Rinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey Sinclair Glick, Kuo Tung Chang