Patents by Inventor Tung Lin

Tung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318447
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Publication number: 20160081775
    Abstract: A bone implant drill includes a bearing received in a sleeve. A transmission shaft includes a rod extending through the bearing and a transmission member formed on an end of the rod and received in the sleeve. The other end of the rod extends beyond the sleeve. A cutting rod includes a cutter, a coupling member received in the sleeve, and a positioning member between the cutter and the coupling member. The cutter and the coupling member are provided on two ends of the cutting rod respectively. The coupling member includes second teeth releasably engageable with first teeth on a free end of the transmission member. An elastic element is mounted in the sleeve. The elastic element includes a first end mounted around the coupling member and abutting the positioning member. The elastic element further includes a second end mounted around the transmission member and abutting the bearing.
    Type: Application
    Filed: January 27, 2015
    Publication date: March 24, 2016
    Inventors: Tung-Lin Tsai, E-Hsung Cheng, Bo-Wei Pan, Pei-Hua Wang
  • Patent number: 9287170
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Teng-Chun Tsai, Li-Ting Wang, Chi-Yuan Chen, Cheng-Tung Lin, Chi-Hsuan Ni, Chia-Han Lai, Wei-Jung Lin, Huicheng Chang, Huang-Yi Huang
  • Publication number: 20160066436
    Abstract: A method for fabricating a circuit board structure is provided. The method includes providing a first circuit board and a second circuit board, wherein the area of the second circuit board is less than the area of the first circuit board. The first circuit board and the second circuit board are combined by a surface mount technology to form the circuit board structure having a portion with a different number of layers.
    Type: Application
    Filed: December 10, 2014
    Publication date: March 3, 2016
    Inventors: Tung-Lin Chuang, Chi-Yi Yen
  • Patent number: 9268923
    Abstract: Systems and methods for application identification in accordance with embodiments of the invention are disclosed. In one embodiment, a user device includes a processor and memory configured to store an application, a session manager, an application identifier, and at least one shared library, and the processor is configured by the session manager to communicate the application identifier and the application identifier data to an authentication server and permit the execution of the application in response to authentication of the application by the authentication server.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: February 23, 2016
    Assignee: Sonic IP, Inc.
    Inventors: Eric William Grab, Kourosh Soroushian, Tung Lin, Francis Yee-Dug Chan, Evan Wallin, William David Amidei
  • Patent number: 9257362
    Abstract: A heat dissipation module configured on a substrate having a heat producing element thereon includes a holder configured on the substrate and a heat sink having a base opposite to the heat producing element and pivotally connected to the holder and capable of joining to the substrate with the heat producing element covered by the base.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: February 9, 2016
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Wen Chi Hung, Tung Lin Tsai, Wen Ke Huang, Bo Han Huang, Tzu Chun Su
  • Publication number: 20160027917
    Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 28, 2016
    Inventors: CHENG-TUNG LIN, TENG-CHUN TSAI, LI-TING WANG, DE-FANG CHEN, BING-HUNG CHEN, HUANG-YI HUANG, HUI-CHENG CHANG, HUAN-JUST LIN, MING-HSING TSAI
  • Publication number: 20160020180
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: CHIH-TANG PENG, TAI-CHUN HUANG, TENG-CHUN TSAI, CHENG-TUNG LIN, DE-FANG CHEN, LI-TING WANG, CHIEN-HSUN WANG, HUAN-JUST LIN, YUNG-CHENG LU, TZE-LIANG LEE
  • Publication number: 20160008103
    Abstract: A dental prosthesis includes an implanting end, a coupling end, and a screw portion between the implanting end and the coupling end. The dental prosthesis further includes a positioning marker portion located adjacent to the coupling end of the dental prosthesis. The dental prosthesis can be precisely located in an alveolar bone of a patient. A dental implant includes the dental prosthesis and an abutment. The abutment includes a prosthesis coupling end. The prosthesis coupling end of the abutment is coupled to the coupling end of the dental prosthesis.
    Type: Application
    Filed: August 25, 2014
    Publication date: January 14, 2016
    Inventors: Tung-Lin Tsai, Bo-Wei Pan, Yi-Chin Chen, Pei-Hua Wang
  • Publication number: 20160005922
    Abstract: A light emitting component includes a light emitting unit, a phosphor layer and a distributed Bragg reflector layer. The phosphor layer is disposed on the light emitting unit and the distributed Bragg reflector layer is disposed above the phosphor layer. The distributed Bragg reflector layer is formed by at least two materials with different refractive indices.
    Type: Application
    Filed: November 9, 2014
    Publication date: January 7, 2016
    Inventors: Kuan-Chieh Huang, Shao-Ying Ting, Tung-Lin Chuang, Jing-En Huang, Yi-Ru Huang
  • Patent number: 9224833
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Publication number: 20150364358
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: TENG-CHUN TSAI, LI-TING WANG, DE-FANG CHEN, CHENG-TUNG LIN, CHIH-TANG PENG, CHIEN-HSUN WANG, BING-HUNG CHEN, HUAN-JUST LIN, YUNG-CHENG LU
  • Publication number: 20150364360
    Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHING-FENG FU, CHENG-TUNG LIN, LI-TING WANG, CHIH-TANG PENG
  • Publication number: 20150364333
    Abstract: According to an exemplary embodiment, a method of forming vertical structures is provided. The method includes the following operations: providing a substrate; forming a first oxide layer over the substrate; forming a first dummy layer over the first oxide layer; etching the first oxide layer and the first dummy layer to form a recess; forming a second dummy layer in the recess (and further performing CMP on the second dummy layer and stop on the first dummy layer); removing the first dummy layer; removing the first oxide layer; and etching the substrate to form the vertical structure. According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; an STI embedded in the substrate; and a vertical transistor having a source substantially aligned with the STI.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHIH-TANG PENG
  • Publication number: 20150357432
    Abstract: Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 10, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHENG-TUNG LIN, TENG-CHUN TSAI, LI-TING WANG, DE-FANG CHEN, CHIH-TANG PENG, HUNG-TA LIN, CHIEN-HSUN WANG, HUANG-YI HUANG
  • Patent number: 9199659
    Abstract: A retractable rack includes a connecting part, a holding mount, a first support element, a second support element and a positioning mechanism. The connecting part may detachably attach to a stroller frame. The second support element is retractably mounted on the opposite side of the holding mount and capable of selectively locking in a first position and a second position relative to the first support element. The positioning mechanism is mounted in the holding mount for locking the second support element in the positions. When the second support element is locked in the first position, the retractable rack is capable of supporting and connecting a car seat with a first size, and when the second support element is locked in the second position, the retractable rack is capable of supporting another car seat with a second size to the stroller frame.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 1, 2015
    Assignee: LERADO (ZHONG SHAN) INDUSTRIAL CO., LTD
    Inventors: Lung-Sheng Chen, Yu-Tung Lin, Ho-Sheng Chen
  • Publication number: 20150333152
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHENG-TUNG LIN, TENG-CHUN TSAI, LI-TING WANG, DE-FANG CHEN, HUANG-YI HUANG, HUI-CHENG CHANG, HUAN-JUST LIN, MING-HSING TSAI
  • Patent number: 9184360
    Abstract: A light-emitting device of the invention includes a base, at least one light-emitting element, a wavelength transferring cover and a heat-conducting structure. The light-emitting element is disposed on the base and electrically connected to the base. The wavelength transferring cover is disposed on the base and covers the light-emitting element. The heat-conducting structure is disposed on the base and directly contacts the wavelength transferring cover.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 10, 2015
    Assignee: Genesis Photonics Inc.
    Inventors: Cheng-Yen Chen, Yi-Fan Li, Han-Min Wu, Kuan-Chieh Huang, Tung-Lin Chuang, Sheng-Yuan Sun
  • Publication number: 20150318214
    Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.
    Type: Application
    Filed: August 14, 2014
    Publication date: November 5, 2015
    Inventors: Teng-Chun TSAI, Cheng-Tung LIN, Li-Ting WANG, Chih-Tang PENG, De-Fang CHEN, Hung-Ta LIN, Chien-Hsun WANG
  • Publication number: 20150318213
    Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 5, 2015
    Inventors: Teng-Chun TSAI, Li-Ting WANG, Cheng-Tung LIN, De-Fang CHEN, Chih-Tang PENG, Chien-Hsun WANG, Hung-Ta LIN