Patents by Inventor Tung Lin
Tung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9980791Abstract: An orthodontic remodeling device includes a sleeve having first and second screw holes in two ends thereof. The first and second screw holes have opposite thread directions. A first screw rod includes a first threaded portion threadedly engaged with the first screw hole and a first assembling portion exposed outside of the sleeve. A second screw hole includes a second threaded portion threadedly engaged with the second screw hole and a second assembling portion exposed outside of the sleeve. Two tooth pushing members are respectively engaged with the first and second assembling portions. Each tooth pushing member includes at least one tooth coupling ring mounted on at least one tooth of a patient for pushing the at least one tooth outward. The sleeve is rotatable to move the first and second screw rods toward or away from each other to change a relative position between the two tooth pushing members.Type: GrantFiled: April 19, 2017Date of Patent: May 29, 2018Assignee: Metal Industries Research & Development CentreInventors: Yue-Jun Wang, Tung-Lin Tsai, Chun-Chieh Tseng, Li-Wen Weng, Chih-Lung Lin
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Publication number: 20180130926Abstract: An LED includes a first-type semiconductor layer, a light emitting layer, a second-type semiconductor layer, a first metal layer, a first current conducting layer, a first bonding layer, and a second current conducting layer. The light emitting layer is located between the first-type semiconductor layer and the second-type semiconductor layer. The first metal layer is located on the first-type semiconductor layer and electrically connected to the first-type semiconductor layer. The first metal layer is located between the first current conducting layer and the first-type semiconductor layer. The first current conducting layer is located between the first bonding layer and the first metal layer. The first bonding layer is electrically connected to the first-type semiconductor layer via the first current conducting layer and the first metal layer. The first bonding layer has through holes overlapping with the first metal layer.Type: ApplicationFiled: October 6, 2017Publication date: May 10, 2018Applicant: Genesis Photonics Inc.Inventors: Yi-Ru Huang, Sheng-Tsung Hsu, Yu-Chen Kuo, Chih-Ming Shen, Tung-Lin Chuang, Tsung-Syun Huang, Jing-En Huang
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Patent number: 9966448Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.Type: GrantFiled: May 16, 2014Date of Patent: May 8, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
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Patent number: 9954069Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.Type: GrantFiled: March 30, 2016Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
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Patent number: 9941394Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.Type: GrantFiled: August 14, 2014Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng, De-Fang Chen, Hung-Ta Lin, Chien-Hsun Wang
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Publication number: 20180055646Abstract: A femur supporting device includes a femoral stem having a plurality of inclined passages. The femoral stem includes an inner side and an outer side. Each inclined passage includes an outlet in the inner side and an inlet in the outer side. Each inclined passage inclines upward from the inlet to the outlet. A plurality of supporting rods extends through the inclined passages. A first engaging end of each supporting rod extends out of the outlet of one of the inclined passages. A second engaging end of each supporting rod extends out of the inlet of one of the inclined passages. The first engaging end of each supporting rod is engaged with one of a plurality of first engaging portions in a trochanter head. The second engaging end of each supporting rod is engaged with one of a plurality of second engaging portions of a fixing unit.Type: ApplicationFiled: May 3, 2017Publication date: March 1, 2018Inventors: Tung-Lin Tsai, Chia-Lung Li, Shih-Hua Huang, Pei-Hua Wang, Chun-Chieh Tseng, Yue-Jun Wang, Li-Wen Weng
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Patent number: 9899258Abstract: Overhang reduction methods are disclosed. In some embodiments, a method includes forming a recess in a dielectric layer, the recess defining first sidewalls of the dielectric layer. The method also includes depositing a first conductive layer over an upper surface of the dielectric layer and the sidewalls of the dielectric layer, the first conductive layer having a first overhang, removing the first overhang of the first conductive layer using an etchant selected from the group consisting of a halide of the first conductive layer, Cl2, BCl3, SPM, SC1, SC2, and combinations thereof, and filling the recess with a second conductive layer.Type: GrantFiled: September 30, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Wen Wu, Sung-Li Wang, Min-Hsiu Hung, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi On Chui
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Publication number: 20180033687Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.Type: ApplicationFiled: July 29, 2016Publication date: February 1, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiu HUNG, Sung-Li WANG, Pei-Wen WU, Yida LI, Chih-Wei CHANG, Huang-Yi HUANG, Cheng-Tung LIN, Jyh-Cherng SHEU, Yee-Chia YEO, Chi-On CHUI
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Patent number: 9883594Abstract: A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.Type: GrantFiled: July 13, 2017Date of Patent: January 30, 2018Assignee: Subtron Technology Co., Ltd.Inventors: Yu-Chi Huang, Kuo-Tung Lin
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Publication number: 20180019232Abstract: A light emitting component includes an epitaxial structure, an adhesive layer, a first reflective layer, a second reflective layer, a block layer, a first electrode and a second electrode. The epitaxial structure includes a substrate, a first semiconductor layer, a light emitting layer and a second semiconductor layer. The adhesive layer is disposed on the second semiconductor layer of the epitaxial structure. The first reflective layer is disposed on the adhesive layer. The second reflective layer is disposed on the first reflective layer and extended onto the adhesive layer. A projection area of the second reflective layer is larger than a projection area of the first reflective layer. The block layer is disposed on the second reflective layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer.Type: ApplicationFiled: September 25, 2017Publication date: January 18, 2018Applicant: Genesis Photonics Inc.Inventors: Yi-Ru Huang, Tung-Lin Chuang, Chih-Ming Shen, Sheng-Tsung Hsu, Kuan-Chieh Huang, Jing-En Huang
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Publication number: 20170374039Abstract: Systems and methods for application identification in accordance with embodiments of the invention are disclosed. In one embodiment, a user device includes a processor and memory configured to store an application, a session manager, an application identifier, and at least one shared library, and the processor is configured by the session manager to communicate the application identifier and the application identifier data to an authentication server and permit the execution of the application in response to authentication of the application by the authentication server.Type: ApplicationFiled: August 21, 2017Publication date: December 28, 2017Applicant: Sonic IP, Inc.Inventors: Eric William Grab, Kourosh Soroushian, Tung Lin, Francis Yee-Dug Chan, Evan Wallin, William David Amidei
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Patent number: 9853102Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.Type: GrantFiled: August 8, 2014Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Li-Ting Wang, Cheng-Tung Lin, De-Fang Chen, Chih-Tang Peng, Chien-Hsun Wang, Hung-Ta Lin
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Publication number: 20170345765Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
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Patent number: 9805968Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.Type: GrantFiled: February 13, 2017Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Bing-Hung Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
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Publication number: 20170311005Abstract: A method of wireless audio transmission and playback includes steps of: a) dividing, by a host, the audio data into audio segments; b) transmitting, by the host, the audio segments to each of audio playback devices; c) transmitting to the host, by each of the audio playback devices, with respect to each of the audio segments received thereby, an acknowledgment indicating that the audio playback device has received the audio segment; and d) when determining, by the host based on the acknowledgment(s) thus received, that at least one of the audio playback devices has received a first specific audio segment, controlling all of the audio playback devices having received the first audio segment to play the first audio segment synchronously with each other.Type: ApplicationFiled: April 25, 2017Publication date: October 26, 2017Inventor: Szu-Tung LIN
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Publication number: 20170311450Abstract: A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.Type: ApplicationFiled: July 13, 2017Publication date: October 26, 2017Applicant: Subtron Technology Co., Ltd.Inventors: Yu-Chi Huang, Kuo-Tung Lin
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Publication number: 20170309787Abstract: A light emitting diode (LED) having distributed Bragg reflector (DBR) and a manufacturing method thereof are provided. The distributed Bragg reflector is used as a reflective element for reflecting the light generated by the light emitting layer to an ideal direction of light output. The distributed Bragg reflector has a plurality of through holes, such that the metal layer and the transparent conductive layer disposed on two sides of the distributed Bragg reflector may contact each other to conduct the current. Due to the distribution properties of the through holes, the current may be more uniformly diffused, and the light may be more uniformly emitted from the light emitting layer.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Inventors: Yi-Ru Huang, Kuan-Chieh Huang, Chih-Ming Shen, Tung-Lin Chuang, Hung-Chuan Mai, Jing-En Huang, Shao-Ying Ting
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Patent number: 9794233Abstract: Systems and methods for application identification in accordance with embodiments of the invention are disclosed. In one embodiment, a user device includes a processor and memory configured to store an application, a session manager, an application identifier, and at least one shared library, and the processor is configured by the session manager to communicate the application identifier and the application identifier data to an authentication server and permit the execution of the application in response to authentication of the application by the authentication server.Type: GrantFiled: February 8, 2016Date of Patent: October 17, 2017Assignee: Sonic IP, Inc.Inventors: Eric William Grab, Kourosh Soroushian, Tung Lin, Francis Yee-Dug Chan, Evan Wallin, William David Amidei
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Publication number: 20170287569Abstract: An electronic apparatus and a data verification method using the same are provided. The electronic apparatus includes a first read-only memory having first data, a second read-only memory having second data and a controller. A correspondence relation exists between the first data and the second data. The controller is coupled to the first read-only memory and the second read-only memory. The controller reads first sub-data of the first data from the first read-only memory, and reads second sub-data of the second data corresponding to the first sub-data from the second read-only memory according to the correspondence relation. The first sub-data includes to-be-verified data. The controller performs a verification operation to the to-be-verified data according to the first sub-data, the second sub-data and the correspondence relation.Type: ApplicationFiled: June 29, 2016Publication date: October 5, 2017Inventors: Jeng-Shiun Liu, Chun-Chih Lin, Tung-Lin Lu
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Patent number: 9779831Abstract: An electronic apparatus and a data verification method using the same are provided. The electronic apparatus includes a first read-only memory having first data, a second read-only memory having second data and a controller. A correspondence relation exists between the first data and the second data. The controller is coupled to the first read-only memory and the second read-only memory. The controller reads first sub-data of the first data from the first read-only memory, and reads second sub-data of the second data corresponding to the first sub-data from the second read-only memory according to the correspondence relation. The first sub-data includes to-be-verified data. The controller perfoi ins a verification operation to the to-be-verified data according to the first sub-data, the second sub-data and the correspondence relation.Type: GrantFiled: June 29, 2016Date of Patent: October 3, 2017Assignee: Wistron CorporationInventors: Jeng-Shiun Liu, Chun-Chih Lin, Tung-Lin Lu