Patents by Inventor Van H. Le

Van H. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083359
    Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.
    Type: Application
    Filed: June 29, 2017
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady
  • Patent number: 10580882
    Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Matthew V. Metz, Van H. Le, Seiyon Kim, Benjamin Chu-Kung
  • Publication number: 20200066515
    Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 27, 2020
    Inventors: Van H. LE, Benjamin CHU-KUNG, Willy RACHMADY, Marc C. FRENCH, Seung Hoon SUNG, Jack T. KAVALIEROS, Matthew V. METZ, Ashish AGRAWAL
  • Publication number: 20200066912
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Rafael RIOS, Shriram SHIVARAMAN, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC
  • Publication number: 20200066326
    Abstract: A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.
    Type: Application
    Filed: December 23, 2015
    Publication date: February 27, 2020
    Inventors: Rafael RIOS, Gilbert DEWEY, Van H. LE, Jack KAVALIEROS, Mesut METERELLIYOZ
  • Publication number: 20200058705
    Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey
  • Publication number: 20200058798
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Application
    Filed: December 24, 2016
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Publication number: 20200035683
    Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Inte Corpooration
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Publication number: 20200035839
    Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Shriram Shivaraman, Van H. Le, Abhishek A. Sharma, Gilbert W. Dewey, Benjamin Chu-Kung, Miriam R. Reshotko, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200027883
    Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Ravi Pillarisetty, Gilbert W. Dewey, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Tahir Ghani
  • Publication number: 20200027504
    Abstract: In one embodiment, systems, methods, and apparatus are described that can reduce the peak current through semiconductor memory devices such as RRAM devices. In one embodiment, transition metal dichalcogenide (TMD) materials can be used to in connection with both the transistors and the memory (for example, RRAM) devices. In one embodiment, two-dimensional (2D) materials, that is, materials that are on the order of a few angstroms thick can be used in connection with both the transistors and the memory (for example, RRAM) devices. In one embodiment, the TMD layer(s) and/or the 2D material(s) can act as a ballast to the RRAM device that can control the current flow through the RRAM device. In one embodiment, the systems, methods, and apparatus can serve to reduce the current as the voltage increases at a predetermined range, a property that can be referred to as negative differential resistance (NDR).
    Type: Application
    Filed: December 30, 2016
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert Dewey
  • Publication number: 20200020805
    Abstract: Disclosed are systems, methods, and apparatus directed to the fabrication of vertical field effect transistors (VFETs) and VFETs with self-aligned wordlines. In one embodiment, the source and/or drain of the VFETs can include n-doped silicon. In one embodiment, the VFETs can include a channel that can be made of intrinsic silicon. In one embodiment, the source, drain, and/or channel can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD), and the like. In one embodiment, an STI process can be used to fabricate one or more recesses, which can reach the drains of the VFETs. In one embodiment, the systems, methods, and apparatus can permit the self-alignment of one or more wordlines of the VFETs with the one or more fins, and/or gate metals and gate materials of the VFETs.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady
  • Publication number: 20200013861
    Abstract: Substrates, assemblies, and techniques for a backend transistor, where the backend transistor includes a gate, a semiconductor oxide, a source metal and a drain metal, and an insulator between the source metal and the gate and between the drain metal and the gate. The insulator can allow for tunneling between the source metal and/or the drain metal and the semiconductor oxide.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Shriram Shivaraman, Tahir Ghani, Jack T. Kavalieros, Cory E. Weber
  • Publication number: 20200006572
    Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Abhishek A. SHARMA, Yih WANG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Nazila HARATIPOUR, Benjamin CHU-KUNG, Seung Hoon SUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Matthew V. METZ
  • Publication number: 20200006229
    Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.
    Type: Application
    Filed: October 28, 2016
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: SEUNG HOON SUNG, GLENN A. GLASS, VAN H. LE, ASHISH AGRAWAL, BENJAMIN CHU-KUNG, ANAND S. MURTHY, JACK T. KAVALIEROS
  • Publication number: 20200006570
    Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Van H. LE, Rajat PAUL, Abhishek SHARMA, Tahir GHANI, Jack KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20200006575
    Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Gilbert DEWEY, Aaron LILAK, Van H. LE, Abhishek A. SHARMA, Tahir GHANI, Willy RACHMADY, Rishabh MEHANDRU, Nazila HARATIPOUR, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Seung Hoon SUNG, Shriram SHIVARAMAN
  • Publication number: 20200006573
    Abstract: Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Aaron LILAK, Van H. LE, Abhishek A. SHARMA, Tahir GHANI, Rishabh MEHANDRU, Gilbert DEWEY, Willy RACHMADY
  • Publication number: 20200006388
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Gilbert DEWEY, Patrick MORROW, Aaron LILAK, Willy RACHMADY, Anh PHAN, Ehren MANNEBACH, Hui Jae YOO, Abhishek SHARMA, Van H. LE, Cheng-Ying HUANG
  • Publication number: 20190393223
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Application
    Filed: March 31, 2017
    Publication date: December 26, 2019
    Inventors: Abhishek Anil SHARMA, Van H. LE, Gilbert William DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Yih WANG, Shriram SHIVARAMAN