Patents by Inventor Wei-An HSIEH

Wei-An HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446448
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Chun-Tsen Lu, Shou-Wei Hsieh
  • Patent number: 10416566
    Abstract: A method to improve a lithographic process of imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including: computing a multi-variable cost function, the multi-variable cost function being a function a plurality of design variables that represent characteristics of the lithographic process; and reconfiguring one or more of the characteristics of the lithographic process by adjusting one or more of the design variables until a certain termination condition is satisfied; wherein a bandwidth of a radiation source of the lithographic apparatus is allowed to change during the reconfiguration.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 17, 2019
    Assignees: ASML NETHERLANDS B.V., CYMER, LLC
    Inventors: Willard Earl Conley, Wei-An Hsieh, Tsann-Bim Chiou, Cheng-Hsien Hsieh
  • Patent number: 10364503
    Abstract: A medical gas-liquid supply system including an electrolytic gas generator, a pure water supply device, a control unit, a first gas storing unit, a second gas storing unit and a gas output unit is provided. The control unit is electrically connected to the electrolytic gas generator for controlling the voltage value of the electrolytic gas generator and the type of gases generated by the electrolytic gas generator. The first and second gas storing units are communicated to the electrolytic gas generator for storing the first and second gases generated by the electrolytic gas generator respectively. The gas output unit is communicated to the first and second gas storing units and has first, second and third output ends for outputting the first gas, a mixed gas and the second gas respectively, in which the mixed gas includes the first and second gases.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 30, 2019
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Guo-Bin Jung, Chia-Chen Yeh, Jyun-Wei Yu, Chia-Ching Ma, Chung-Wei Hsieh
  • Patent number: 10347761
    Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Chun-Jung Tang, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10340272
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Shou-Wei Hsieh, Hsin-Yu Chen
  • Publication number: 20190189525
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 20, 2019
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10310563
    Abstract: An accessory suitable for an electronic device is provided. The electronic device has a display area. The accessory includes a coupling portion and a cover portion. The coupling portion is suitable to be coupled to the electronic device. The cover portion is connected to the coupling portion and is suitable for covering the display area of the electronic device. The cover portion has a plurality of light-transmitting areas, and the light-transmitting areas are arranged on the display area in an array. An image generated by the display area is projected out of the cover portion through the light-transmitting areas. Moreover, an electronic assembly containing the electronic device and the accessory is also provided. Furthermore, a control method is also provided for controlling the electronic assembly. A method is also provided for forming an accessory.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: June 4, 2019
    Assignee: HTC Corporation
    Inventors: Yen-Hung Lin, Chien-Wei Hsieh, Chun-Ta Huang, Hung-Chuan Wen, Michael Ross Massucco
  • Publication number: 20190157443
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.
    Type: Application
    Filed: December 20, 2017
    Publication date: May 23, 2019
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Publication number: 20190131453
    Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.
    Type: Application
    Filed: November 24, 2017
    Publication date: May 2, 2019
    Inventors: Chun-Hao Lin, Chun-Jung Tang, Hsin-Yu Chen, Shou-Wei Hsieh
  • Publication number: 20190131134
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Hong-Ying LIN, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sean Lo, C.W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Patent number: 10266410
    Abstract: A preparation method of battery composite material includes steps of providing a manganese-contained compound, phosphoric acid, a lithium-contained compound, a carbon source, and deionized water; processing a reaction of the manganese-contained compound, the phosphoric acid, and a portion of the deionized water to produce a first product; placing the first product at a first temperature for at least a first time period to produce a first precursor, wherein the chemical formula of the first precursor is written by Mn5(HPO4)2(PO4)2(H2O)4; and processing a reaction of at least the first precursor, the lithium-contained compound, and another portion of the deionized water, adding the carbon source, and then calcining to produce battery composite material. Therefore, the preparation time is shortened, the energy consuming is reduced, the phase forming of the precursor is more stable, and the advantages of reducing the cost of preparation and enhancing the quality of products are achieved.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 23, 2019
    Assignee: ADVANCED LITHIUM ELECTROCHEMISTRY CO., LTD.
    Inventors: Hsiang-Pin Lin, Han-Wei Hsieh, An-Feng Huang, Chun-Ming Huang
  • Patent number: 10262223
    Abstract: A method of speeding up image detection, adapted to increase a speed of detecting a target image and enhance efficiency of image detection, comprises the steps of capturing an image; retrieving a plurality of characteristic points of the image; creating a region of interest (ROI) centered at the characteristic points each; creating a plurality of search point scan windows corresponding to the ROIs, respectively; calculating target hit scores of the characteristic points and the search point scan windows; comparing the target hit scores of the characteristic points and the search point scan windows to obtain an ROI most likely to have a target image; calculating centroid coordinates of the ROI by a centroid shift weight equation; and narrowing a scope of ROI search according to a location of the centroid coordinates and reducing a displacement between the search points.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 16, 2019
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chun-Wei Hsieh, Shih-Che Chien, Feng-Chia Chang, Chien-Hao Hsiao
  • Patent number: 10256160
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10244780
    Abstract: A food preservation system is provided. The system includes a storage cabinet for storing foods, an electrolytic gas generator, a gas sensor and a control unit. The electrolytic gas generator is in fluid communication with the storage cabinet to output a first gas and a second gas to preserve the foods. The gas sensor is arranged in the storage cabinet to detect the concentration of the gases in the storage cabinet for obtaining gas concentration information which includes a first gas concentration and a second gas concentration. The control unit is electrically connected to the electrolytic gas generator and the gas sensor. According to the received gas concentration information, the control unit adjusts the applied voltage of the electrolytic gas generator to control the gas species generated by the electrolytic gas generator and the first and second gas concentrations in the storage cabinet.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: April 2, 2019
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Guo-Bin Jung, Chia-Chen Yeh, Jyun-Wei Yu, Chia-Ching Ma, Chung-Wei Hsieh, Cheng-Lung Lin, Kuan-Fu Liao, Jing-Yu Hu
  • Patent number: 10246355
    Abstract: An aquaculture system is provided. The aquaculture system includes a cultivation pond, a water circulation unit, a water quality detector, and a water processing module. The cultivation pond for storing the cultivation water has a recirculation inlet and recirculation outlet. The water circulation unit is in fluid communication with the cultivation pond to allow the cultivation water in the cultivation pond to circulate through the water circulation unit. The water quality detector is used to detect the quality of the water to obtain water quality information. The water processing module includes an electrolytic gas generator and a control unit to improve the quality of water. The control unit receives the water quality information and adjusts the applied voltage on the electrolytic gas generator according to the water quality information to control the gas species and a ratio of the gases generated by the electrolytic gas generator.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: April 2, 2019
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Guo-Bin Jung, Chia-chen Yeh, Jyun-Wei Yu, Chia-Ching Ma, Chung-Wei Hsieh, Cheng-Lung Lin
  • Publication number: 20190096771
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.
    Type: Application
    Filed: October 18, 2017
    Publication date: March 28, 2019
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Publication number: 20190083322
    Abstract: A negative pressure wound dressing is provided. The negative pressure wound dressing sequentially includes a barrier layer, an indicating layer, a liquid impermeable, a liquid impermeable, gas permeable layer, an absorbent layer and a wound contacting layer, wherein, the barrier layer comprises a connecting hole for fluidly connecting a negative pressure source, and the indicating layer comprises at least one visual indicating element on the surface adjacent to the barrier layer. By using the negative pressure wound dressing of the present invention, the user can be reminded to replace the dressing timely by the visual indicating element which can detect the wound exudates absorption in the absorbing layer to effectively improve the wound healing.
    Type: Application
    Filed: March 19, 2018
    Publication date: March 21, 2019
    Inventors: Mao-Sung Huang, Huai-Wei Hsieh
  • Patent number: 10228800
    Abstract: The present invention provides a method and device for position detection. For detection of a touch position, a segment of surface acoustic wave (SAW) is provided multiple times to be propagated on a SAW touch panel, and the multiple SAW segments are received by the SAW touch panel. In addition, during or after reception, partial output electrical signals are provided based on different portions of each received SAW segment to construct a complete output electrical signal.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 12, 2019
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Shang-Tai Yeh, Teng-Wei Hsieh
  • Publication number: 20190074051
    Abstract: A refresh control method for a memory system is provided. The memory system includes a dynamic random access memory with a register set and a memory cell array. The refresh control method includes the following steps. Firstly, a masking command or an unmasking command is issued, and thus the register set is updated. A first region of the memory cell array is set as a masked region according to the masking command. A second region of the memory cell array is set as an unmasked region according to the unmasking command. Then, a refresh command is issued to the dynamic random access memory. According to the refresh command, a refresh action is performed on the second region of the memory cell array.
    Type: Application
    Filed: June 1, 2018
    Publication date: March 7, 2019
    Inventors: Chia-Fu CHANG, Hsiang-I HUANG, Bo-Wei HSIEH, Szu-Ying CHENG, Yu-Hsien TSAI
  • Publication number: 20190067118
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Chun-Tsen Lu, Shou-Wei Hsieh