Patents by Inventor Wei-An HSIEH

Wei-An HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210335786
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
    Type: Application
    Filed: July 5, 2021
    Publication date: October 28, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • DRAM, MEMORY CONTROLLER AND ASSOCIATED TRAINING METHOD
    Publication number: 20210295894
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Application
    Filed: April 22, 2021
    Publication date: September 23, 2021
    Applicant: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210280744
    Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Wei HSIEH, Cheng-Yuan KUNG
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210265280
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210249369
    Abstract: A semiconductor device package includes a carrier, an emitting device, a first building-up circuit and a first package body. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The emitting element is disposed on the first surface of carrier. The first building-up circuit is disposed on the second surface of the carrier. The first package body encapsulates the lateral surface of the carrier.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Wei HSIEH, Chieh-Chen FU
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210249367
    Abstract: A semiconductor device package includes an emitting device and a first building-up circuit. The emitting device defines a cavity in the emitting device. The first building-up circuit is disposed on the emitting device.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Wei HSIEH
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210249368
    Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Wei HSIEH, Kuo-Chang KANG
  • Method for enlarging tip portion of a fin-shaped structure
    Patent number: 11088137
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Contact structure
    Patent number: 11062908
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • SEMICONDUCTOR DEVICE
    Publication number: 20210210628
    Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210210423
    Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Meng-Wei HSIEH, Teck-Chong LEE
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210202406
    Abstract: A semiconductor device package includes a first circuit layer and an emitting device. The first circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device is disposed on the second surface of the first circuit layer. The emitting device has a first surface facing the second surface of the first circuit layer, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device has a conductive pattern disposed on the second surface of the emitting device. The lateral surface of the emitting device and the lateral surface of the first circuit layer are discontinuous.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Meng-Wei HSIEH
  • Angle sensing device
    Patent number: 11041708
    Abstract: An angle sensing device including a first object, a second object, a magnetic field source, and a first magnetic sensor is provided. The second object is adapted to be rotated with respect to the first object, so that an inclined angle of the second object with respect to the first object is changed. The magnetic field source is connected to the second object. The first magnetic sensor is connected to the first object, and configured to sense a magnetic field generated by the magnetic field source. When the second object is rotated with respect to the first object, the magnetic field sensed by the first magnetic sensor changes, so that an output signal of the first magnetic sensor corresponding to the magnetic field changes.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: June 22, 2021
    Assignee: iSentek Inc.
    Inventors: Wei-An Hsieh, Fu-Te Yuan, Yen-Chi Lee
  • DELAY TRACKING METHOD AND MEMORY SYSTEM
    Publication number: 20210174851
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Applicant: Media Tek Inc.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210167189
    Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.
    Type: Application
    Filed: January 29, 2021
    Publication date: June 3, 2021
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210159322
    Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 27, 2021
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • DRAM, memory controller and associated training method
    Patent number: 11017839
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 25, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
  • Semiconductor device
    Patent number: 10991824
    Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • EXTENSIBLE MEMORY DUAL INLINE MEMORY MODULE
    Publication number: 20210109849
    Abstract: Disclosed herein is an extensible memory subsystem comprising a dual in-line memory module (DIMM) that includes a dynamic random-access memory (DRAM) having a basic memory space, a DIMM memory controller coupled to the DRAM, a memory interface configured to couple the DIMM to a DIMM connector of a computing device, and a first extension interface configured to couple the DIMM to a first remote memory module having a first remote memory space, wherein the DIMM memory controller is configured to map a DIMM memory space comprising the basic memory space of the DRAM and the first remote memory space of the first remote memory module, the DIMM memory space being accessible by the computing device upon the DIMM being coupled to the computing device via the memory interface, and a first remote memory module coupled to the DIMM via the first extension interface of the DIMM.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 15, 2021
    Inventors: Yu-Wei Hsieh, Po Chia Chen, Li-Ping Zhang, Tai Wei Hsia
  • Delay tracking method and memory system
    Patent number: 10964363
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 30, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen