Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.

Abstract: A flyback power converter converts an input power on a primary side into an output power on a secondary side. On the secondary side, the output power is monitored to provide a representative signal representing a characteristic of the output power. A count is kept unchanged when a clock ticks if the representative signal is within a first range defined in accordance with a target value, that the representative signal is going to be regulated at. The count is changed in response to the clock if the representative signal is within a second range different from the first range. In response to the count, a driving current is generated to control a coupler, which generates a compensation signal on the primary side that controls power transmitted from the primary side to the secondary side.

Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

Abstract: An anti-glare substrate, an anti-reflection film, and a display device are disclosed. The anti-glare substrate includes a first surface and a second surface disposed on opposite sides. The first surface includes a plurality of protrusion structures. Each protrusion structure includes a plurality of inclined planes. There is an angle ? between the normal direction of each inclined plane and the normal direction of the second surface. The sum of the vertical projection area of the inclined planes with ? less than 2.5° on the second surface is A<2.5, wherein the vertical projection area of the inclined planes is AT, wherein A < 2.5 A T ? 100 ? % ? 3.58 % . The anti-reflection film is for use with an anti-glare substrate. For a first assembly formed by disposing the anti-reflection film on the anti-glare substrate, the reflectances to blue ray, to green ray, and to red ray are close. The display device includes the anti-glare substrate and a display panel.

Abstract: A biological feature identification device includes a display device and a sensing device. The display device includes multiple pixels arranged along a first direction. The pixels each has a sub-pixel having a display element and a switch element. The sensing device includes multiple sensing units arranged along a second direction. The sensing units each has a sensing element. When the spatial frequency relation is |4*(RE/100)?(1/SU)|>A, the first and second directions are the same, and the biological feature identification device satisfy the criteria: A<|4*(RE/100)?(1/SU)|<B. When the spatial frequency relation is |4*(RE/100)?(1/SU)|?A, the first and second directions form an angle, and the biological feature identification device satisfy the criteria: A<|4*(RE/100)?{1/[SU*Cos(?)]}|<C. RE is the resolution of the display device, SU is the sensing unit size, ? is the angle, 0°<?<90°, B and C>A, and A is not equal to zero.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: A preparation method of a cathode material for a secondary battery is provided. First, a lithium metal phosphate material and a first conductive carbon are provided. The lithium metal phosphate material is made of a plurality of secondary particles. Each of the secondary particles is formed by the aggregation of a plurality of primary particles. An interparticle space is formed between the plurality of primary particles. Next, the lithium metal phosphate material and the first conductive carbon are mixed by a mechanical method, and a composite material is prepared. The first conductive carbon is uniformly arranged in the interparticle space. After that, a second conductive carbon, a binder and a solvent are provided. Finally, the composite material, the second conductive carbon, the binder and the solvent are mixed, and a cathode material for preparing a positive plate is prepared.

Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

Abstract: A semiconductor device package includes a first circuit layer and an emitting device. The first circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device is disposed on the second surface of the first circuit layer. The emitting device has a first surface facing the second surface of the first circuit layer, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device has a conductive pattern disposed on the second surface of the emitting device. The lateral surface of the emitting device and the lateral surface of the first circuit layer are discontinuous.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A fingerprint recognition device including a light emitting layer, an image sensing layer and a micro-lens layer is provided. The image sensing layer has a plurality of pixels. The micro-lens layer is disposed between the light emitting layer and the image sensing layer and has a plurality of micro lenses respectively corresponding to the pixels. A distance between the micro-lens layer and the light emitting layer is less than or equal to 800 um and greater than or equal to h1, where h1=(x/2×tan ?), x is the minimum distance between two micro lenses respectively corresponding to different pixels on a plane where the micro-lens layer is disposed, and ? is an FWHM light receiving angle of each of the micro lenses.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a carrier, an element, and a first electronic component. The element is disposed on the carrier. The first electronic component is disposed above the element. The element is configured to adjust a first bandwidth of a first signal transmitted from the first electronic component.

Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.

Abstract: The present disclosure provides an antenna module. The antenna module includes a first layer, a second layer, a first antenna, and a second antenna. The first layer has a first dielectric constant. The second layer is adjacent to the first layer. The second layer has a second Dk lower than the first Dk. The first antenna is disposed on the first layer and is configured for operating at a first frequency. The second antenna is disposed on the second layer and is configured for operating at a second frequency higher than the first frequency.

Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.

Abstract: A testing method for determining radiation performance of a device under test (DUT) is disclosed. The testing method comprises the following steps. The DUT is arranged at a first orientation. A first effective isotropic radiated power (EIRP) and a first effective isotropic sensitivity (EIS) of the DUT are measured at the first orientation. The DUT is arranged at a second orientation different from the first orientation, and a second EIRP of the DUT is measured at the second orientation. A second EIS of the DUT is measured at the second orientation according to a correlation between the first EIRP, the first EIS and the second EIRP.

Abstract: An optical sensing device includes a substrate, a sensing element layer, a light-shielding layer, and a light absorbing layer. The substrate has a first surface and a second surface opposite to each other. The sensing element layer is disposed on the first surface and includes multiple sensing elements. The light-shielding layer is disposed on the sensing element layer and has multiple openings. An orthogonal projection of the opening on the substrate overlaps an orthogonal projection of the sensing element on the substrate. The light absorbing layer is disposed on the second surface. An electronic apparatus including the optical sensing device is also provided.

Abstract: A fingerprint recognition device including a light emitting layer, an image sensing layer and a micro-lens layer is provided. The image sensing layer has a plurality of pixels. The micro-lens layer is disposed between the light emitting layer and the image sensing layer and has a plurality of micro lenses respectively corresponding to the pixels. A distance between the micro-lens layer and the light emitting layer is less than or equal to 800 um and greater than or equal to h1, where h1=x/(2×tan ?), x is the minimum distance between two micro lenses respectively corresponding to different pixels on a plane where the micro-lens layer is disposed, and ? is an FWHM light receiving angle of each of the micro lenses.