Patents by Inventor Wei Lu

Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063204
    Abstract: Integrated circuit package structures and methods of forming integrated circuit package structures are discussed. An integrated circuit package structure, in accordance with some embodiments, includes an integrated circuit package substrate with a heterogeneous bonding scheme that includes conductive pillars for bonding semiconductor devices to as well as a region including conductive connectors embedded in a dielectric for bonding additional semiconductor devices.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Chung-Shi Liu
  • Publication number: 20240063043
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer with multiple semiconductor dies on the adhesive film held by the frame element. The method also includes lifting a semiconductor die up from the wafer using an ejector element. The method includes picking up the semiconductor die with a collector element. The method further includes flip-chipping the semiconductor die with the collector element, and picking up the semiconductor die from the collector element using a bond-head element. In addition, the method includes measuring the warpage of the semiconductor die on the bond-head element using a sensor, then bonding the semiconductor die to a carrier using the bond-head element.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Jung CHEN, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Patent number: 11909396
    Abstract: An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Jiun-Wei Lu
  • Publication number: 20240050726
    Abstract: Microneedle arrays for introducing an active ingredient through a skin surface of a subject can include a base layer, a plurality of microneedles projecting from the base layer, and an active ingredient. Each of the microneedles comprises an elongate body having a proximal portion and a distal portion, in which the proximal portion is attached to the base layer. Each of the microneedles comprises at least one dissolvable polymer. The active ingredient is incorporated in the elongate body, and the active ingredient is present only in the distal portion and at least internally in the distal portion.
    Type: Application
    Filed: March 19, 2023
    Publication date: February 15, 2024
    Applicant: Allergan, Inc.
    Inventors: Futian LIU, Xiaojie YU, Lance E. STEWARD, Guang Wei LU, Patrick M. HUGHES, Seshadri NEERVANNAN
  • Publication number: 20240055410
    Abstract: A package structure is provided. The package structure includes a substrate and a semiconductor chip over the substrate. The package structure also includes a protective frame laterally surrounding the semiconductor chip. The package structure further includes an underfill element between the semiconductor chip and the protective frame. A portion of the underfill element is directly below the protective frame.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 15, 2024
    Inventors: Chen-Hsuan TSAI, Tsung-Fu TSAI, Shih-Ting LIN, Szu-Wei LU
  • Patent number: 11901255
    Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20240041363
    Abstract: The invention relates to an optoelectronic system. The optoelectronic system includes an optoelectronic probe operably attached to a target region of a subject; and an electronic module coupled with the optoelectronic probe for wireless, real-time, and continuous measurements of physiological information of the subj ect.
    Type: Application
    Filed: November 10, 2021
    Publication date: February 8, 2024
    Inventors: John A. Rogers, Wei Lu, Joseph M. Forbess, Zhi-Dong Ge
  • Publication number: 20240047598
    Abstract: The present disclosure relates to an infrared photodetector based on a van der waals heterostructure and a preparation method thereof. The infrared photodetector comprises a fully depleted van der waals heterostructure. The fully depleted van der waals heterostructure comprises a first n-type two-dimensional semiconductor layer, a p-type two-dimensional semiconductor layer, and a second n-type two-dimensional semiconductor layer which are sequentially provided from bottom to top. A fully depleted built-in electric field is formed by means of a sandwich structure including the first n-type two-dimensional semiconductor layer, the p-type two-dimensional semiconductor layer and the second n-type two-dimensional semiconductor layer, which can improve the light absorption efficiency while reducing the dark current of a device, and the separation rate and collection efficiency of photo-induced carriers are accelerated.
    Type: Application
    Filed: November 21, 2022
    Publication date: February 8, 2024
    Inventors: FANG WANG, FUXING DAI, WEIDA HU, XIAOSHUANG CHEN, WEI LU
  • Publication number: 20240047272
    Abstract: A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: I-MING CHANG, CHUNG-LIANG CHENG, HSIANG-PI CHANG, HUNG-CHANG SUN, YAO-SHENG HUANG, YU-WEI LU, FANG-WEI LEE, ZIWEI FANG, HUANG-LIN CHAO
  • Publication number: 20240047238
    Abstract: The present disclosure relates to load cups that include an annular substrate station configured to receive a substrate. The annular substrate station surrounds a nebulizer located within the load cup. The nebulizer includes a set of energized fluid nozzles disposed on an upper surface of the nebulizer adjacent to an interface between the annular substrate station and the nebulizer. The set of energized fluid nozzles are configured to release energized fluid at an upward angle relative to the upper surface.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Inventors: Wei LU, Jimin ZHANG, Jianshe TANG, Brian J. BROWN
  • Patent number: 11894287
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11883923
    Abstract: A method of chemical mechanical polishing includes rotating a polishing pad about an axis of rotation, positioning a substrate against the polishing pad, the polishing pad having a groove that is concentric with the axis of rotation, oscillating the substrate laterally across the polishing pad such that a central portion of the substrate and an edge portion of the substrate are positioned over a polishing surface of the polishing pad for a first duration, and holding the substrate substantially laterally fixed in a position such that the central portion of the substrate is positioned over the polishing surface of the polishing pad and the edge portion of the substrate is positioned over the groove for a second duration.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: January 30, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Jimin Zhang, Jianshe Tang, Brian J. Brown, Wei Lu, Priscilla Diep LaRosa
  • Patent number: 11882871
    Abstract: A detachable atomizing device and a container thereof are provided. The container is detachably assembled to an atomizing assembly. The container includes a cup and a flexible film. The cup has an opening arranged at an end thereof, the flexible film covers the opening of the cup, and the flexible film has a tension region and an outer ring-shaped region that surrounds the tension region. The tension region has a plurality of atomizing holes having an average diameter within a range of 1 ?m to 20 ?m, and the outer ring-shaped region is attached to the cup. When the cup is assembled to the atomizing assembly, a tension value of the tension region of the flexible film is increased from an initial tension value to an atomizing tension value by being pressed from the atomizing assembly, and the atomizing holes of the tension region are configured to allow liquid to pass there-through and to be formed as aerosol mist having an average atomized particle diameter less than a predetermined value.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 30, 2024
    Assignee: MICROBASE TECHNOLOGY CORP.
    Inventors: Chih-Wei Lu, Chen-Hsiang Sang, Liang-Rern Kung, Wei-Zhe Cai, Jo-Ling Wu, Shu-Pin Hsieh
  • Publication number: 20240027281
    Abstract: A drive system thermal temperature rise test and compensation system. The system has an optical non-contact type sensing head mounted on a main shaft of a machine tool, and a sensing center is formed in the center of the sensing head. A platform driven by a transmission device of the machine tool is provided with plural ball lens devices, and a temperature sensor for transmitting temperature data externally is further provided on the transmission device. After the machine tool sequentially records an original point coordinate for each ball lens center by using the sensing head, the sensing head is cyclically and sequentially moved to the original point coordinate of each ball lens, so as to measure a displacement error between the sensing center and the ball lens center resulted from thermal shifts of the transmission device, as well as capable of measuring multiaxial errors and using various axial temperatures for compensation.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 25, 2024
    Inventors: Wen-Yuh JYWE, Tung-Hsien HSIEH, Chia-Ming HSU, Yu-Wei CHANG, Sen-Yi HUANG, Ching-Ying CHIU, Pin-Wei LU, Jheng-Jhong ZENG
  • Publication number: 20240019280
    Abstract: A sensing device (10) for a high voltage disconnecting switch (20). The sensing device (10) comprises: a first optical fiber (110) configured to receive light from an optical source (100) and configured to guide the light; an optical collimator (120) coupled to the first optical fiber (110) to receive the light guided in the first optical fiber (110) and configured to collimate the light into a collimated light beam; a bendable optical component (130) coupled to the optical collimator (120) to receive the collimated light beam and configured to guide the collimated light beam, wherein the bendable optical component (130) is configured and arranged to bend depending on a switching state of the high voltage disconnecting switch (20), thereby influencing the collimated light beam; and a deriving unit (160) configured to derive information about the switching state of the high voltage disconnecting switch (20) based on the collimated light beam.
    Type: Application
    Filed: November 5, 2020
    Publication date: January 18, 2024
    Applicant: Weinert Industries AG
    Inventors: Hakan Sayinc, Oliver Gross, Juntao Deng, Wei Lu
  • Publication number: 20240021442
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: August 1, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20240014162
    Abstract: A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240016064
    Abstract: A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih-Wei LU, Chung-Ju LEE
  • Patent number: D1014616
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 13, 2024
    Assignee: Zebra Technologies Corporation
    Inventors: Anthony Ross Helberg, Wei Lu