Patents by Inventor Wei Wu

Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098182
    Abstract: Aspects of this disclosure are directed to a method and a terminal device, and a computer-readable storage medium. The terminal device includes processing circuitry that obtains n voice messages from at least one user account. n is a positive integer. The processing circuitry displays a voice message presentation interface. The voice message presentation interface is configured to display virtual characters corresponding to the n voice messages in a virtual world. Locations of the n voice messages in the virtual world are based on whether the n voice messages are unplayed. The virtual characters can be based on respective message attributes of the n voice messages.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Wei DAI, Kun LU, Qinghua ZHONG, Jun WU, Yingren WANG, Rong HUANG
  • Publication number: 20240094538
    Abstract: The present disclosure provides a near-eye display device and a construction method for a meta lens. The near-eye display device includes a substrate (10), a meta lens array (40) provided on the side of the substrate (10) close to an eye (100), and a pixel island array (30) located on the side of the substrate (10) away from the eye (100). The pixel island array (30) includes a plurality of pixel islands. The meta lens array (40) includes a plurality of meta lenses. The orthographic projection of the lens center of the meta lens on the substrate (10) overlaps the orthographic projection of the pixel center of the pixel island on the substrate. The lens center is the geometric center of the meta lens, and the pixel center is the geometric center of the pixel island.
    Type: Application
    Filed: December 27, 2021
    Publication date: March 21, 2024
    Inventors: Weiting PENG, Qiuyu LING, Wei WANG, Xianqin MENG, Pengxia LIANG, Qian WU
  • Publication number: 20240095141
    Abstract: A method and an apparatus for displaying an information flow on a terminal device, an electronic device, a computer-readable storage medium, and a computer program product are provided. An implementation is: in response to detecting an activation operation on an application for displaying the information flow, reproducing, on the terminal device, a first page displayed on the terminal device when the application is last switched to running in the background or closed; and in response to determining that a time interval between the activation operation and the application being last switched to running in the background or closed does not exceed a first threshold, displaying a second page as a continuation of a content entry displayed in the first page, where the second page includes at least one first content entry cached in the terminal device before the activation operation but not displayed in the first page.
    Type: Application
    Filed: March 21, 2022
    Publication date: March 21, 2024
    Inventors: Yifan ZHANG, Yuqi WANG, Linfei CHU, Jing NING, Kunjie SUN, Yuhang ZHENG, Naifei SONG, Shujuan ZHANG, Lin LIU, Xunzhuo JU, Zhengwei CHEN, Wei ZHANG, Hua ZHANG, Congjun ZHOU, Tingkang WU, Tengfei LV, Hanmeng LIU, Lei WANG
  • Publication number: 20240096848
    Abstract: A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Wei Wu, Ching-Feng Yang, Ying-Ching Shih, An-Jhih Su, Wen-Chih Chiou
  • Publication number: 20240097067
    Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
  • Publication number: 20240097747
    Abstract: Apparatuses, systems, and methods for multi-TRP by a UE, including out of order delivery of PDSCH, PUSCH, and/or DL ACK/NACK. The UE may receive, from a base station, a configuration that may include multiple control resource set (CORESET) pools and each CORESET pool may be associated with an index value. The UE may determine that at least two DCIs of the multiple DCIs end at a common symbol and determine, based on one or more predetermined rules, when the UE may be scheduled to receive PDSCHs, transmit PUSCHs, and/or transmit ACK/NACKs from CORESETs associated with the at least two DCIs.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Haitong Sun, Yushu Zhang, Wei Zeng, Dawei Zhang, Yuchul Kim, Hong He, Weidong Yang, Chunhai Yao, Chunxuan Ye, Oghenekome Oteri, Ismael Gutierrez Gonzalez, Ghaith N Hattab, Jie Cui, Yang Tang, Haijing Hu, Fangli Xu, Zhibin Wu, Yuqin Chen, Yeong-Sun Hwang
  • Publication number: 20240098746
    Abstract: The present application relates to devices and components including apparatus, systems, and methods to provide reduced sensing schemes to facilitate sidelink transmissions.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Apple Inc.
    Inventors: Chunxuan Ye, Dawei Zhang, Haijing Hu, Haitong Sun, Hong He, Jia Tang, Oghenekome Oteri, Weidong Yang, Zhibin Wu, Wei Zeng
  • Publication number: 20240099154
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Publication number: 20240097641
    Abstract: A resonator includes a resonance layer, a substrate, and a barrier layer. The barrier layer is located on the substrate, and the barrier layer and the substrate form a cavity. The cavity is configured to accommodate the resonance layer. The barrier layer includes a top wall and a side wall, and an inner surface of the side wall surrounds the resonance layer. An outer surface of the side wall includes a groove, and the groove surrounds the side wall.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Wei Wu, Hao Li, Jinhui Wang, Wei Li
  • Publication number: 20240097746
    Abstract: Apparatuses, systems, and methods for multi-TRP by a UE, including out of order delivery of PDSCH, PUSCH, and/or DL ACK/NACK. The UE may receive, from a base station, a configuration that may include multiple control resource set (CORESET) pools and each CORESET pool may be associated with an index value. The UE may determine that at least two DCIs of the multiple DCIs end at a common symbol and determine, based on one or more predetermined rules, when the UE may be scheduled to receive PDSCHs, transmit PUSCHs, and/or transmit ACK/NACKs from CORESETs associated with the at least two DCIs.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Haitong Sun, Yushu Zhang, Wei Zeng, Dawei Zhang, Yuchul Kim, Hong He, Weidong Yang, Chunhai Yao, Chunxuan Ye, Oghenekome Oteri, Ismael Gutierrez Gonzalez, Ghaith N. Hattab, Jie Cui, Yang Tang, Haijing Hu, Fangli Xu, Zhibin Wu, Yuqin Chen, Yeong-Sun Hwang
  • Publication number: 20240097817
    Abstract: Methods, systems, and devices for wireless communication are described to support replacing values of one or more information bit vectors with one or more corresponding sets of parity bits. A first wireless device may replace an information bit vector with a parity bit vector, using a set of information bits of the information bit vector and based on a parity check matrix, which may result in generating the set of information bits at an information bit vector corresponding to a parity bit column of the parity check matrix, during encoding. The first wireless device may perform a transmission to a second wireless device, which may receive the transmission, decode the set of information bits to the information bit vector corresponding to the parity bit column. The second wireless device may replace other bit estimates of a vector corresponding to an information bit column with the set of information bits.
    Type: Application
    Filed: March 18, 2021
    Publication date: March 21, 2024
    Inventors: Wei LIU, Thomas Joseph RICHARDSON, Liangming WU, Changlong XU, Ori SHENTAL, Hao XU
  • Publication number: 20240096941
    Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 21, 2024
    Inventors: SHIH-JUNG TU, PO-WEI LIU, TSUNG-YU YANG, YUN-CHI WU, CHIEN HUNG LIU
  • Patent number: 11936645
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 19, 2024
    Assignee: Kingston Digital, Inc.
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11934610
    Abstract: A touch control method is provided. The touch control method is applied in a touch device including a plurality of touch electrodes, the touch control method includes: step S1, sending a scanning signal to the plurality of touch electrodes, the scanning signal being a multi-frequency scanning signal; step S2, acquiring touch data according to the multi-frequency scanning signal; and step S3, calculating a current touch position according to the touch data.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 19, 2024
    Assignee: FocalTech Electronics (Shenzhen) Co., Ltd.
    Inventors: Wei-Jing Hou, Jian-Wu Chen, Hui-Dan Xiao, Da-Chun Wu, Zhen-Huan Mou, You-Gang Gong, Guan-Qun Pan
  • Publication number: 20240088209
    Abstract: A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Wei Wu, Yu-Cheng Tung
  • Publication number: 20240089047
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive an indication of an antenna port mapping from a network entity. The antenna port mapping may be between a tracking reference signal and a corresponding reference signal, the antenna port mapping indicating a mapping of a tracking reference signal port to a plurality of reference signal antenna ports associated with the corresponding reference signal. The UE may receive a tracking reference signal via the tracking reference signal port based on the antenna port mapping. The UE may perform a channel measurement procedure using the tracking reference signal based on the mapping.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Jae Won Yoo, Jing Jiang, Wei Yang, Yongle Wu, Vamsi Krishna Amalladinne, Hari Sankar, Alexei Yurievitch Gorokhov
  • Publication number: 20240088019
    Abstract: A connecting structure includes a first dielectric layer, a first connecting via in the first dielectric layer, a second connecting via in the first dielectric layer, and an isolation between the first connecting via and the second connecting via. The isolation separates the first and second connecting vias from each other. The first connecting via, the isolation and the second connecting via are line symmetrical about a central line perpendicular to a top surface of the first dielectric layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: CHIA CHEN LEE, CHIA-TIEN WU, SHIH-WEI PENG, KUAN YU CHEN
  • Publication number: 20240086137
    Abstract: A near eye display system is provided. The near eye display system includes: a frame; a first near eye display mounted on the frame and configured to form a first image directly projected on a first retina of a first eye of a user; a second near eye display mounted on the frame and configured to form a second image directly projected on a second retina of a second eye of the user; and a processing unit located at the frame and configured to generate a display control signal to drive the first near eye display and the second near eye display.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
  • Publication number: 20240090234
    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu