Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Abstract: A display is disclosed. The display comprises a display panel, and an optical film disposed on a viewing side of the display panel. The optical film has a total haze ranging from 15% to 60%, an inner haze less than or equal to 10%, and a reflectivity satisfying the relationships of 0.35%?(RSCI-RSCE)?1.50% and RSCE?1.50%, wherein RSCI is an average reflectivity of diffuse component and specular component, and RSCE is an average reflectivity of diffuse component. By adjusting the total haze, inner haze and reflectivity of the optical film to satisfy the above relationship, the display can have good anti-glare properties, and the contrast ratio of the display will not be reduced too much to avoid the display quality be affected.

Abstract: A display device is configured to determine a target location. The display device includes a waveguide element, a display panel and a processor. The waveguide element is configured to receive an image and reflect the image to an eyeball location. The display panel is located at one side of the waveguide element. The display panel has a plurality of pixel units. The display panel is located between the waveguide element and the target location. The processor is electrically connected to the display panel. The processor is configured to determine the pixel units in a blocking area of the display panel to be opaque. The blocking area of the display panel overlaps the target location. The display panel displays the pixel units in the blocking area as grayscale according to the processor.

Abstract: Systems and methods for simulating subterranean regions having multi-scale, complex fracture geometries in a realistic simulation environment, which includes in the modeling process three-dimensional multi-scale rock discontinuities, hydraulic fractures, and heterogenous reservoir properties. Non-intrusive embedded discrete fracture modeling formulations are applied in conjunction with commercial or in-house simulators to efficiently and accurately model subsurface characteristics including three-dimensional geometries having combinations of complex hydraulic fractures and multi-scale rock discontinuities.

Abstract: A semiconductor structure includes an optical interposer having at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed above the first dielectric layer. The semiconductor structure further includes a first die disposed on the optical interposer and electrically connected to the optical interposer; a first substrate under the optical interposer; and conductive connectors under the first substrate.

Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

Abstract: Disclosed are a point cloud encoding and decoding method and device based on a two-dimensional regularization plane projection. The encoding method includes: acquiring original point cloud data; performing two-dimensional regularization plane projection on the original point cloud data to obtain a two-dimensional projection plane structure; obtaining a plurality of pieces of two-dimensional image information according to the two-dimensional projection plane structure; and encoding the plurality of pieces of two-dimensional image information to obtain code stream information.

Abstract: An electronic component includes a board, an electronic device, and a stiffening structure is provided. The electronic device is disposed on the board. The stiffening structure is disposed on the board. The stiffening structure includes a ring portion corresponding the edge of the board. The stiffening structure includes a core base and a cladding layer. The cladding layer covers the core base.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.

Abstract: Music pushing method, apparatus, electronic device, and storage medium are provided by the embodiments of the present disclosure, for the method, firstly, a user end displays user information that satisfies a preset association relationship with music currently on a music playing interface in response to an operation acting on the music playing interface. In the present embodiments, upon inputting an operation instruction on target music by a user, information of other users who have taken an associated operation instruction to the target music and have an unrestricted friend relationship with the user is displayed, and by presenting music lists corresponding to other users, the user is guided to acquire music pushing information, and thus, ways for the user to acquire the music pushing information are expanded, and problems that music pushing is single and centralized as well as the pushing depends on a friend relationship are overcome.

Abstract: Disclosed herein are RNA methyltransferase inhibitors and methods of using and making the same. The inhibitors may be used in a method for the treatment of a subject in need of a treatment for a cancer by administering an effective amount of the RNA methyltransferase inhibitor and an effective amount of a DNA damaging agent to the subject.

Abstract: A capacitor structure including a substrate, an insulating layer, a capacitor, a shielding layer, a first connection terminal, and a second connection terminal is disposed. The insulating layer is disposed on the substrate. The capacitor includes a first electrode layer, a second electrode layer, a dielectric layer. The first electrode layer is disposed on the insulating layer. The second electrode layer is disposed on the first electrode layer. The dielectric layer is disposed between the first electrode layer and the second electrode layer. The shielding layer is disposed in the insulating layer. The shielding layer is located between the first electrode layer and the substrate. The first connection terminal is electrically connected to the first electrode layer. The second connection terminal is electrically connected to the second electrode layer.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.