Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948987
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11948971
    Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
  • Patent number: 11948949
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
  • Patent number: 11948930
    Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
  • Publication number: 20240103236
    Abstract: A method includes forming an optical engine, which includes a photonic die. The photonic die further includes a grating coupler. The method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. The optical fiber extends into the groove. The fiber platform further includes a reflector. The fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 28, 2024
    Inventors: Chih-Wei Tseng, Jui Lin Chao, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20240102950
    Abstract: A method for determining parameters of nanostructures, wherein the method includes steps as follows: Firstly, an X-ray reflection intensity measurement curve of a nanostructure to be tested is obtained by radiating the nanostructure to be tested with X-ray. The X-ray reflection intensity measurement curve is compared with an X-ray reflection intensity standard curve to obtain a comparison result. Subsequently, at least one parameter existing in the nanostructure to be tested is determined according to the comparison result.
    Type: Application
    Filed: September 28, 2023
    Publication date: March 28, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting LIU, Po-Ching HE, Wei-En FU, Chun-Yu LIU
  • Publication number: 20240105642
    Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Publication number: 20240107682
    Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.
    Type: Application
    Filed: April 21, 2023
    Publication date: March 28, 2024
    Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240104393
    Abstract: Systems and methods for personalized federated learning. The method may include receiving at a central server local models from a plurality of clients, and aggregating a heterogeneous data distribution extracted from the local models. The method can further include processing the data distribution as a linear mixture of joint distributions to provide a global learning model, and transmitting the global learning model to the clients. The global learning model is used to update the local model.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 28, 2024
    Inventors: Wei Cheng, Wenchao Yu, Haifeng Chen, Yue Wu
  • Publication number: 20240103097
    Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 28, 2024
    Inventors: Xin Zheng, Wenjing Yu, Tao Peng, Yi Fang, Ming Lei, Hong Shi, Ben Ma, Li Ding, Wei Wei, Linghua Li, He Yu, Tian Xia, Yingchun Wang, Sike Wang, Dongri Xie, Xin Wang, Bo Pang, Xianjin Rong
  • Publication number: 20240104030
    Abstract: A data bus coupled to a plurality of memory devices is determined to be in a read mode. Responsive to determining that the data bus is in the read mode, a particular read operation identified in a particular memory queue of memory queues that include identifiers of one or more write operations and identifiers of one or more read operations is determined. The particular memory queue includes a highest number of read operations for a memory device of the memory devices. The particular read operation is transmitted from the particular memory queue over the data bus.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Wei Wang, Jiangli Zhu, Ying Yu Tai, Samir Mittal
  • Publication number: 20240107070
    Abstract: Methods, apparatuses, and non-transitory computer-readable storage mediums are provided for video decoding. In one method, a decoder receives a Sequence Parameter Set (SPS) rice extension flag that indicates whether an extension of rice parameter derivation for binarization of abs_remainder and dec_abs_level is enabled. In a second method, the decoder may receive a Sequence Parameter Set (SPS) rice adaption enabled flag that indicates whether rice parameter derivation for binarization of abs_remainder and dec_abs_level is used.
    Type: Application
    Filed: November 25, 2023
    Publication date: March 28, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Hong-Jheng JHU, Xiaoyu XIU, Yi-Wen CHEN, Wei CHEN, Che-Wei KUO, Ning YAN, Xianglin WANG, Bing YU
  • Patent number: 11940597
    Abstract: An image capturing optical lens system includes four lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element and a fourth lens element. The first lens element has an object-side surface being convex in a paraxial region thereof. The third lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The fourth lens element has negative refractive power.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: March 26, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Wei-Yu Chen
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11942857
    Abstract: A power supply is provided. The power supply includes a power supply circuit and a control circuit. The power supply circuit includes a voltage converter and multiple point-of-load circuits. The voltage converter generates a third voltage according to a first voltage. The load point-of-load circuits generate at least one second voltage and at least one state signal according to the third voltage. The at least one second voltage is suitable for supplying power to a load. The control circuit is coupled to the power supply circuit. The control circuit determines whether a single event latch-up occurs in the power supply circuit according to the at least one state signal. When the single event latch-up occurs in the power supply circuit, the control circuit switches off the power supply circuit to stop generating the at least one second voltage and the at least one state signal.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Wei Yang, Chueh-Hao Yu, Chien-Yu Chen
  • Patent number: 11941553
    Abstract: The embodiment of the present disclosure discloses a method, an electronic device, and a storage medium for a ship route optimization. The method for the ship route optimization considers a dynamic feature of a multi-functional emergency rescue ship and an interference effect caused by an airflow, uses a movement model with kinematics non-holonomic constraints, such as a ship total cost assessment function to simulate the movement of the ship, and based on a sparrow search algorithm, learns how to apply the algorithm to a route plan of the emergency rescue ship. The method can improve the ship route optimization algorithm, improve an accuracy and practical applicability of a calculated plan. The method can effectively and accurately locate obstacles and hidden reefs, and consider effects of an airflow and a non-holonomic constraint effect, so as to make the route planning of the ship more efficient and intelligent.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: March 26, 2024
    Assignees: HEFEI UNIVERSITY OF TECHNOLOGY, ANHUI CONSTRUCTION ENGINEERING TRAFFIC & SHIPPING GROUP CO., LTD.
    Inventors: Jingyu Yu, Jingfeng Wang, Wei Lin, Yuxue Pu, Yongchao Zhu, Zhenxuan Li, Qiong Zhang, Yuming Zhang, Yonggen Gu, Zheng Qiu
  • Patent number: 11939280
    Abstract: A method for preparing isophorone diisocyanate by (1) reacting isophorone with hydrogen cyanide in the presence of a catalyst to obtain isophorone nitrile; (2) reacting the isophorone nitrile obtained in step (1) with ammonia gas and hydrogen in the presence of a catalyst to obtain isophorone diamine; and (3) subjecting the isophorone diamine to a phosgenation reaction to obtain the isophorone diisocyanate, wherein the content of impurities containing a secondary amine group in the isophorone diamine that undergoes the phosgenation reaction in step (3) is ?0.5 wt. The method reduces the content of hydrolyzed chlorine in the isophorone diisocyanate product, improves the yellowing resistance of the product, and the harm due to presence of hydrolyzed chlorine in the product is reduced.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: March 26, 2024
    Assignee: WANHUA CHEMICAL GROUP CO., LTD.
    Inventors: Yong Yu, Yonghua Shang, Lei Zhao, Wenbin Li, Ye Sun, Wei He, Xuelei Cui, Jingxu Wang, Degang Liu, Yuan Li
  • Patent number: 11941087
    Abstract: Provided is an unbalanced sample data preprocessing method, which includes: a data acquisition request is received and initial data is acquired according to the data acquisition request, and the initial data is classified according to a preset classification rule to obtain first-class sample sets and second-class sample sets; characteristics of K first sample points extracted are analyzed to obtain a new data characteristic of the first-class sample sets; a new data label of the first-class sample sets is generated according to a first label corresponding to the first-class sample sets; a ratio between the number of first-class sample sets and the number of second-class sample sets is calculated; and new data of the first-class sample sets is generated according to the new data characteristic and the new data label, and the amount of new data is adjusted according to the ratio to increase the number of first-class sample sets.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: March 26, 2024
    Assignee: Ping An Technology (Shenzhen) Co., Ltd.
    Inventors: Xiuming Yu, Wei Wang, Jing Xiao
  • Patent number: 11940605
    Abstract: A photographing optical lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element with refractive power has an object-side surface being convex in a paraxial region thereof. Each second, third, fourth and fifth lens element has refractive power. The sixth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, and both of the surfaces of the sixth lens element are aspheric. The seventh lens element with refractive power has an image-side surface being concave in a paraxial region thereof, wherein the image-side surface has at least one convex shape in an off-axis region thereof.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: March 26, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu Chen
  • Patent number: 11943080
    Abstract: Disclosed is a method for estimating dense multipath parameters by means of multipolarized broadband extended array responses, which includes: first transmitting multiple different transmitted signal sequences via a multipolarized antenna array, and processing received data in multiple snapshots according to the known transmitted signals, to obtain channel responses of multipolarized antenna components at all frequency points in a frequency band; extending the obtained channel response matrixes of multiple frequency points in multiple snapshots into a large two-dimensional channel response matrix; then, acquiring a delay parameter regarding multipath propagation by using a reference array element, and estimating two-dimensional departure and arrival angles by using a channel matrix subjected to frequency domain smoothing and dimensionality reduction; and afterwards, pairing the estimated departure and arrival angles, and estimating parameters such as the cross-polarization ratios, the initial phases, and the
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: March 26, 2024
    Assignee: Southeast University
    Inventors: Haiming Wang, Bensheng Yang, Peize Zhang, Chen Yu, Wei Hong