Abstract: A bridge device having data monitoring function is disclosed. The bridge device can be made to be an integrated circuit (IC) chip, so as to be disposed on a circuit board with a USB connector and a UART connector, thereby forming a USB to UART converter. When using the USB to UART converter, the USB connector is connected to a host computer, and the UART connector is connected to an electronic device. As such, the bridge device provides the host computer with at least three virtual COM ports, such that the host computer is able to conduct a data transmission with the electronic device through one virtual COM port. Moreover, during the data transmission, the host computer is also able to hear the transmitted data by way of diverting the transmitted data through the other two virtual COM ports.

Abstract: A photographing optical lens system includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is convex in a paraxial region thereof. The seventh lens element has negative refractive power. The object-side surface of the seventh lens element is concave in a paraxial region thereof. At least one of all lens surfaces of the seven lens elements is aspheric and has at least one inflection point.

Abstract: This application discloses a network slice information transmission method and apparatus. For example, a controller performs slice division on a network based on a service requirement and then obtains slice information, and sends the slice information to a first network device in the network by using a path computation element protocol (PCEP) packet, which includes first slice information corresponding to the first network device. After receiving the PCEP packet, the first network device parses the PCEP packet to obtain the first slice information, and further performs network slice configuration based on the first slice information. That is, in this application, the controller delivers the slice information by using the PCEP packet, so that after obtaining the PCEP packet, the first network device can obtain the first slice information corresponding to the first network device in a timely manner and perform network slice configuration without waiting for a configuration command.

Abstract: A transparent antenna includes a substrate, an antenna grid layer, and a ground grid layer. The substrate has an electrically conductive hole extending from two opposite surfaced of the substrate. The antenna grid layer is formed on a surface of the substrate. The antenna grid layer includes a feeding portion and a transmission portion. The ground grid layer is formed on another surface of the substrate. The ground grid layer is coupled to the feeding portion of the antenna grid layer via the electrically conductive hole. An offset distance between a projection of a gridline of the antenna grid layer on the first surface and a projection of a gridline of the ground grid layer on the first surface is smaller than or equal to half of a difference between a line width of the antenna grid layer and a line width of the ground grid layer.

Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.

Abstract: The present disclosure provides an image capturing optical system comprising: a positive first lens element having a convex object-side surface; a negative second lens element having a concave object-side surface; a third lens element; a fourth lens element having a convex object-side surface and a concave image-side surface, the object-side surface and the image-side surface thereof being aspheric; a fifth lens element having a concave image-side surface concave, both of the object-side surface and the image-side surface being aspheric, at least one of the object-side surface and the image-side surface having at least one convex shape in an off-axis region thereof.

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

Abstract: Optical data captured in an optical system may be distorted or otherwise affected by various factors, such as but not limited to physical interference, fluorescence, noise or other factors. The effects on the optical data may interfere with any number of uses of the optical data, such as identification, presentation, or the like. Although various embodiments are provided, such as but not limited to spectroscopy, chromatography, and image processing, these are merely example embodiments, and the processing and/or removal of one or more components within the optical data to account for the distortions or other effects. Other applications may include any x, y or x, y, z dataset of optical data.

Abstract: An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

Abstract: A circuit board device includes a transition region that includes a first conductive layer at a first level, a second conductive layer at a second level, and conductive vias. The first conductive layer includes a pad connected to the solderless connector, a transmission line, and a first reference layer. The transmission line includes first and second segments. A second width of the second segment is the same as or less than a first width of the first segment. The first reference layer has a first anti-pad region for the pad and the transmission line disposed therein. In a plan view, the first anti-pad region surrounding the pad is completely located within a second anti-pad region of a second reference layer of the second conductive layer. The conductive vias are disposed between the first and second conductive layers and surround the pad.

Abstract: An optical lens assembly includes seven lens elements which are, in order from object side to image side: first lens element, second lens element, third lens element, fourth lens element, fifth lens element, sixth lens element and seventh lens element. The first lens element has object-side surface having at least one convex shape in off-axis region thereof. The second lens element with positive refractive power has object-side surface being convex in paraxial region thereof. The third lens element has image-side surface being convex in paraxial region thereof. The sixth lens element with positive refractive power has object-side surface being convex in paraxial region thereof. The seventh lens element has image-side surface being concave in paraxial region thereof, and the image-side surface of the seventh lens element has at least one convex critical point in off-axis region thereof. The optical lens assembly has a total of seven lens elements.

Abstract: A diffractive optical assembly includes an input coupler, an output coupler, and an image source. The output coupler is next to the input coupler. One of the input coupler and the output coupler has a most critical holographic optical element (HOE), and another one has a diffractive optical element (DOE). Bragg condition of the most critical HOE is more sensitive than Bragg condition of the DOE. The image source is configured to generate image light that is incident to the input coupler then propagates to the output coupler. The image light has incident angles to the input coupler and wavelengths corresponding to the incident angles. The wavelengths of the image light on the image source have a two-dimensional spatial distribution, such that relationships between the incident angles and the wavelengths of the image light comply with Bragg selectivity of the most critical HOE.

Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

Abstract: The invention provides a light-emitting diode including a plurality of P-type and N-type diode structures, an upper electrode, and a fusion junction. Each of the P-type and N-type diode structures includes a first conductive semiconductor, an active region and a second conductive semiconductor stacked vertically, and the plurality of P-type and N-type diode structures are stacked vertically to form a light emitter. The upper electrode is formed on the light emitter. The fusion junction is located between two of the plurality of P-type and N-type diode structures and formed by fusing the first conductive semiconductor of one of the P-type and N-type diode structure and the second conductive semiconductor of the adjacent P-type and N-type diode structure. The fusion junction includes a non-conductive fusion portion and a plurality of conductive fusion portions dispersed in the non-conductive fusion portion excluding a designated area of the non-conductive fusion portion.

Abstract: A wideband interference mitigation module is coupled to an output of a primary downconverter to process the digital intermediate frequency signal. A selective filtering module is associated with a secondary downconverter that comprises a digital harmonic-resistant translator. The selective filtering module comprises: (a) a low-pass filter that is configured as an anti-aliasing digital filter consistent with a target receive bandwidth to suppress aliasing associated with the analog-to-digital conversion, and (b) narrow band rejection filter to filter the digital baseband signal to reduce or to mitigate electromagnetic interference, where the narrow band rejection filter is configured for adaptive control responsive to detection by the wideband interference mitigation module of certain interference in the received radio frequency signal.

Abstract: The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping and to form multiple devices with different Vt. The method includes forming a gate dielectric layer on a fin structure, forming a buffer layer on the gate dielectric layer, and forming a dopant source layer including a dopant on the buffer layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. The method further includes doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant, removing the dopant source layer and the buffer layer, forming a dopant pulling layer on the gate dielectric layer, and tuning the dopant in the gate dielectric layer by the dopant pulling layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first spacer on a bit line, wherein the first spacer includes low-k material doped with carbon. An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer. The first spacer has a remaining first spacer that is not oxidized by the oxidation process. Then, a second spacer is formed on the oxide spacer, wherein the second spacer includes nitride. The oxide spacer is removed to form a gap between the remaining first spacer and the second spacer. A cover layer is formed to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A compensation circuit is applied to a successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) that includes a comparator, and the comparator includes a first transistor and a second transistor. The first transistor and the second transistor receive an input signal during a sampling phase, and the comparator determines at least one bit of a digital output code during a comparison phase. The compensation circuit includes a voltage generator coupled to the comparator for providing a first voltage to a first bulk of the first transistor and a second bulk of the second transistor during the sampling phase and providing a second voltage to the first bulk of the first transistor and the second bulk of the second transistor during the comparison phase.

Abstract: A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view.