Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088104
    Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Publication number: 20240085669
    Abstract: An optical imaging lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The seventh lens element has an image-side surface being concave in a paraxial region thereof. At least one of an object-side surface and the image-side surface of the seventh lens element has at least one critical point in an off-axis region thereof. The object-side surface and the image-side surface of the seventh lens element are both aspheric.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu CHEN
  • Publication number: 20240088923
    Abstract: Wireless receiver systems and methods for user equipment are described that employ multiple receiver heads. The multiple heads can receive wireless communication signals over different receive paths from different transmission sources. The systems can scan and monitor signal quality from all receiver heads during a scheduled gap in a communication link without interfering with an ongoing communication session.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: MEDIATEK Singapore Pte. Ltd.
    Inventors: Yangjian Chen, Jonathan Richard Strange, Yabo Li, Ganning Yang, Wei-Yu Lai, Wei-Jen Chen
  • Publication number: 20240086329
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Vasileios Porpodas, Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen
  • Publication number: 20240088594
    Abstract: The present application provides a cable connector and an electronic device. The cable connector includes a socket and a plug; the socket is provided with an opening and a connection part for connecting with a circuit board; the plug includes a fixing member and an elastic connection member; the elastic connection member each includes a fixing part and a first elastic contact part connected with the fixing part, the fixing part being fixedly connected with the fixing member for connecting with an inner conductor of the cable; the fixing member is capable of connecting with the socket, and enables the first elastic contact part to elastically contact a signal connection contact on the circuit board through the opening to form electrical connection.
    Type: Application
    Filed: January 22, 2021
    Publication date: March 14, 2024
    Applicant: Zhuhai LinkE Technology Co., Ltd.
    Inventors: Gang Feng, Changming Wu, Yihong Qi, Wei YU
  • Publication number: 20240088205
    Abstract: A capacitor unit includes a bottom electrode; a raised sub-structure provided on the bottom electrode and having a plurality of trenches exposing the bottom electrode; a first capacitance conductive layer formed on a surface of the raised sub-structure and a surface of the bottom electrode, the first capacitance conductive layer having a substantially uniform thickness; a capacitance insulation layer formed on a surface of the first capacitance conductive layer and having a substantially uniform thickness; and a top electrode covering a surface of the capacitance insulation layer. A side of the top electrode abutting the capacitance insulation layer is extended along the surface of the capacitance insulation layer.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: KUO-YU YEH, WEI-YU LIN
  • Publication number: 20240088155
    Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Patent number: 11929261
    Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 11926787
    Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignees: PetroChina Company Limited, CNPC Engineering Technology R&D Company Limited
    Inventors: Shuoqiong Liu, Hua Zhang, Jianzhou Jin, Ming Xu, Yongjin Yu, Fengzhong Qi, Congfeng Qu, Hong Yue, Youcheng Zheng, Wei Li, Yong Ma, Youzhi Zheng, Zhao Huang, Jinping Yuan, Zhiwei Ding, Chongfeng Zhou, Chi Zhang, Zishuai Liu, Hongfei Ji, Yuchao Guo, Xiujian Xia, Yong Li, Jiyun Shen, Huiting Liu, Yusi Feng, Bin Lyu
  • Patent number: 11925146
    Abstract: The present disclosure provides a cultivation method of morels and belongs to the technical field of cultivation of edible fungi. After nutrient contents that can be metabolized and utilized by morel mycelia are scientifically matched, sterilization treatment of exogenous nutrients is eliminated, and the exogenous nutrients are directly compressed for forming. Formed exogenous nutrient blocks and spawn is sowed and covered with soil, so as to realize a potential difference between “rich” and “poor” nutrients in a physical space. When the spawn germinate to form a mycelium network, the mycelia will enter a nutrient-rich exogenous nutrient area, secrete various extracellular enzymes to decompose and utilize these exogenous nutrient blocks, and transport them to a nutrient-poor mycelium network for storage, so as to complete nutrient assimilation and absorption, and reserve energy for later sexual reproduction.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: March 12, 2024
    Assignee: Kunming Institute of Botany, Chinese Academy of Sciences
    Inventors: Xiaofei Shi, Wei Liu, Yingli Cai, Fuqiang Yu
  • Publication number: 20240081154
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao
  • Publication number: 20240077762
    Abstract: A display is disclosed. The display comprises a display panel, and an optical film disposed on a viewing side of the display panel. The optical film has a total haze ranging from 15% to 60%, an inner haze less than or equal to 10%, and a reflectivity satisfying the relationships of 0.35%?(RSCI-RSCE)?1.50% and RSCE?1.50%, wherein RSCI is an average reflectivity of diffuse component and specular component, and RSCE is an average reflectivity of diffuse component. By adjusting the total haze, inner haze and reflectivity of the optical film to satisfy the above relationship, the display can have good anti-glare properties, and the contrast ratio of the display will not be reduced too much to avoid the display quality be affected.
    Type: Application
    Filed: April 10, 2023
    Publication date: March 7, 2024
    Applicant: BenQ Materials Corporation
    Inventors: Yu-Wei Tu, Chih-Wei Lin, Kuo-Hsuan Yu
  • Publication number: 20240077726
    Abstract: A display device is configured to determine a target location. The display device includes a waveguide element, a display panel and a processor. The waveguide element is configured to receive an image and reflect the image to an eyeball location. The display panel is located at one side of the waveguide element. The display panel has a plurality of pixel units. The display panel is located between the waveguide element and the target location. The processor is electrically connected to the display panel. The processor is configured to determine the pixel units in a blocking area of the display panel to be opaque. The blocking area of the display panel overlaps the target location. The display panel displays the pixel units in the blocking area as grayscale according to the processor.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 7, 2024
    Inventors: Yeh-Wei YU, Ko-Ting CHENG, Pin-Duan HUANG, Ching-Cherng SUN
  • Publication number: 20240077669
    Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 7, 2024
    Inventors: Chen-Hua Yu, Jiun Yi Wu, Szu-Wei Lu
  • Publication number: 20240080497
    Abstract: Disclosed are a point cloud encoding and decoding method and device based on a two-dimensional regularization plane projection. The encoding method includes: acquiring original point cloud data; performing two-dimensional regularization plane projection on the original point cloud data to obtain a two-dimensional projection plane structure; obtaining a plurality of pieces of two-dimensional image information according to the two-dimensional projection plane structure; and encoding the plurality of pieces of two-dimensional image information to obtain code stream information.
    Type: Application
    Filed: February 7, 2022
    Publication date: March 7, 2024
    Applicant: Honor Device Co., Ltd.
    Inventors: Fuzheng YANG, Wei ZHANG, Yuxin DU, Zexing SUN, Youguang YU, Tian CHEN, Ke ZHANG
  • Publication number: 20240076980
    Abstract: Systems and methods for simulating subterranean regions having multi-scale, complex fracture geometries in a realistic simulation environment, which includes in the modeling process three-dimensional multi-scale rock discontinuities, hydraulic fractures, and heterogenous reservoir properties. Non-intrusive embedded discrete fracture modeling formulations are applied in conjunction with commercial or in-house simulators to efficiently and accurately model subsurface characteristics including three-dimensional geometries having combinations of complex hydraulic fractures and multi-scale rock discontinuities.
    Type: Application
    Filed: September 4, 2022
    Publication date: March 7, 2024
    Applicants: PetroChina Southwest Oil & Gas Field Company, ZFRAC LLC, BJ Karst Science & Technology Ltd.
    Inventors: Rui Yong, Jianfa Wu, Joseph Alexander Leines Artieda, Cheng Chang, Jijun Miao, Wei Yu, Hongbing Xie
  • Publication number: 20240079324
    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie CHEN, Ying-Ju CHEN, Chen-Hua YU, Der-Chyang YEH, Hsien-Wei CHEN
  • Publication number: 20240077670
    Abstract: A semiconductor structure includes an optical interposer having at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed above the first dielectric layer. The semiconductor structure further includes a first die disposed on the optical interposer and electrically connected to the optical interposer; a first substrate under the optical interposer; and conductive connectors under the first substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: March 7, 2024
    Inventors: Chih-Wei Tseng, Hsing-Kuo Hsia, Stefan Rusu, Chen-Hua Yu, Chewn-Pu Jou
  • Publication number: 20240079486
    Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Ting CHANG, Ching Yu CHEN, Jiang-He XIE
  • Patent number: D1017230
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: March 12, 2024
    Inventor: Wei Yu