Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

Abstract: An adhesion film with a plurality of semiconductor packages thereupon may be positioned on a pedestal including an enclosure and having a perforated top surface, a first support ring located at a periphery of the perforated top surface, and a second support ring laterally surrounding the first support ring. A first semiconductor package overlaps segments of the first support ring at a plurality of overlap areas in a top-down view, and does not contact the second support ring in the top-down view. A vacuum suction may be applied to a volume within the enclosure and to a gap which is vertically bounded by a bottom surface of the adhesion film and is laterally bounded by the first support ring while holding the first semiconductor package stationary. A portion of the adhesion film underlying the first semiconductor package is peeled off a bottom surface of the first semiconductor package.

Abstract: A semiconductor package structure includes a semiconductor die encapsulated in a molding compound, a redistribution structure over the semiconductor die and the molding compound, a surface device over and electrically connected to the redistribution structure, a first connector over and electrically connected to the redistribution structure, a second connector between the surface device and the redistribution structure, a trench in the redistribution structure and laterally surrounding the surface device in a top view of the semiconductor package structure, and an underfill. The second connector electrically connects the surface device to the redistribution structure. The underfill surrounds the second connector. The underfill include a first portion and a second portion. The first portion of the underfill is located between the surface device and the redistribution structure and laterally surrounding the second connector, and the second portion of the underfill is disposed in the trench.

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: An electronic device is provided. The electronic device includes a first subscriber identity module (SIM), a second SIM, and a processor. The processor is configured to merge a first signal from the first SIM and a second signal from the second SIM and transmit the first signal and the second signal through a radio frequency front end (RFFE) transmission path concurrently, in response to a determination that the first signal and the second signal are intra-band signals and the first SIM and the second SIM share one RFFE transmission path.

Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.

Abstract: A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view.

Abstract: A double-sided plush fabric formed by knitting with a circular knitting machine, the double-sided plush fabric includes a basic structure and two plush structures respectively connected to the basic structure and positioned on two opposite sides of the basic structure, each of the two plush structures includes a plurality of cut-loop piles, and a length of the cut-loop piles of the two plush structures is in a range from 3.5 mm to 15 mm, each of the two plush structures includes a plurality of arcuate yarn segments connected with the basic structure, one of the two plush structures is connected to two of the cut-loop piles by the continuous arcuate yarn segments, and the other one of the two plush structures is connected to two of the cut-loop piles by one of the arcuate yarn segments.

Abstract: An image lens assembly includes five lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The third lens element has negative refractive power. The fourth lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof. The fifth lens element has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The image-side surface of the fifth lens element includes at least one convex critical point in an off-axis region thereof.

Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

Abstract: A low-temperature continuous-flow preparation method of bedaquiline includes the following steps. (a) A first feed liquid and a second feed liquid are subjected to a first continuous flow reaction for 30-600 seconds to obtain a first reaction mixture. (b) The first reaction mixture and a third feed liquid are subjected to a second continuous flow reaction for 30-600 seconds to obtain a second reaction mixture. (c) The second reaction mixture was quenched to afford bedaquiline.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

Abstract: The present application relates to the technology field of assessment of aging state of oil paper insulation of the large power transformer and quantitative diagnostic, specifically estimating parameters of the circuit through the initial slope of the recovery voltage. It includes an improved mathematical model for solving parameters of the dielectric response equivalent circuit by using the peak of the recovery voltage, the peak time and the initial slope characteristics; transforming the identification of parameters of the equivalent circuit into a mathematical optimization problem, and then solving the mathematical optimization problem using a particle swarm algorithm. The design of the present application can significantly reduce the sampling data of the recovery voltage, and the measured data in the field and the calculated data of different capacity RVM experiments on real transformers have good consistency, which is conducive to the diagnosis of state of oil paper insulation of the transformer.

Abstract: A photographing lens assembly includes eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof. The seventh lens element has an image-side surface being concave in a paraxial region thereof. The eighth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, and the image-side surface of the eighth lens element has at least one critical point in an off-axis region thereof.