Patents by Inventor Wei Yu

Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387509
    Abstract: An integrated circuit including: substrates stacked one over another, the substrates including first to fourth substrates having a P-type doping; the first substrate including a first set of electrical components on one or more of the substrates and forming a first circuit; a first ground reference rail connected to the first circuit; a first power supply rail connected between the first power supply rail and the first ground reference rail; a first electrostatic discharge (ESD) conduction element, connected between the first ground reference rail and a first part of a common ground reference rail, including a first diode in the second substrate and a second diode in the first substrate; the first diode and the second diode being connected in parallel, having different dopant types and having opposite polarities; and a second part of the common ground reference rail being connected to the third substrate and the fourth substrate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Wei Yu MA, Chia-Hui CHEN, Kuo-Ji CHEN
  • Publication number: 20240387245
    Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Hua Yu, Wei-Yu Chen, Jiun Yi Wu, Chung-Shi Liu, Chien-Hsun Lee
  • Publication number: 20240387431
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Publication number: 20240385472
    Abstract: The invention provides a display device including a display panel and a backlight module including a light guide plate, a light source, and an optical film. The light guide plate has light incident and exit surfaces. The light source is disposed at one side of the light incident surface. The optical film is overlapped with the light exit surface, and has first optical microstructures facing the light exit surface. The display panel includes a liquid crystal cell overlapped with the light exit surface, first and second polarizers respectively disposed at two opposite sides of the liquid crystal cell, and a phase retardation film disposed between the first and second polarizers. The first polarizer is located between the liquid crystal cell and the optical film. An axial direction of an optical axis of the phase retardation film is inclined with respect to a thickness direction of the first phase retardation film.
    Type: Application
    Filed: June 27, 2024
    Publication date: November 21, 2024
    Applicant: Coretronic Corporation
    Inventors: Ping-Yen Chen, Chung-Yang Fang, Jen-Wei Yu
  • Patent number: 12146587
    Abstract: The present invention provides a flow control switch including a pipeline structure, a rotating structure, a position-limiting structure and a knob structure. The pipeline structure includes a tubular body and a ball body rotatably disposed in the tubular body. The rotating structure includes a rotatable element connected to the ball body for driving the ball body to rotate. The position-limiting structure is disposed on the tubular body. The knob structure is liftably disposed on the rotating structure for cooperating with the rotatable element. The position-limiting structure has a first and a second position-limiting groove. The knob structure includes a knob body liftably disposed on the rotatable element and a position-limiting element detachably disposed on the knob body. The position-limiting element is optionally disposed in one of the first and the second position-limiting groove, so as to limit a rotation of the rotatable element relative to the position-limiting structure.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: November 19, 2024
    Assignee: RAYZHER INDUSTRIAL CO., LTD
    Inventors: Ku-Hua Chou, Yen-Cheng Chen, Shih Wei Yu
  • Publication number: 20240379035
    Abstract: An adjustment method of screen brightness comprises the following steps. Step (a): obtaining a relationship between a brightness and refresh rate of the screen. Step (b): adjusting the screen to a highest refresh rate and displaying an image at a first brightness. Step (c): decreasing the first brightness by a unit brightness value and variably displaying the image between a first refresh rate and a second refresh rate. Step (d): determining whether the image does not flicker; if not, repeating step (c). Step (e): calculating a first brightness difference between a decreased brightness of the screen and a brightness corresponding to a lowest refresh rate when the image does not flicker. Step (f): determining whether the first brightness difference is less than a screen flicker threshold; if yes, decreasing the first brightness corresponding to the highest refresh rate to obtain an adjusted brightness corresponding to the highest refresh rate.
    Type: Application
    Filed: January 10, 2024
    Publication date: November 14, 2024
    Applicant: Qisda Corporation
    Inventors: Yi-Zong JHAN, Tse-Wei FAN, Chun-Chang WU, Jen-Hao LIAO, Wei-Yu CHEN, Feng-Lin CHEN, Fu-Tsu YEN
  • Patent number: 12142682
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai, Ming-Te Chen
  • Patent number: 12144065
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Publication number: 20240370221
    Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.
    Type: Application
    Filed: November 17, 2023
    Publication date: November 7, 2024
    Inventors: Hui HUANG, Chia-Wei YU, Tien-Hung LIN, Jiamei FENG
  • Publication number: 20240370222
    Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. The first input data includes K columns, the first part includes 1st to Mth columns of the first input data, and the second part includes Nth to Kth columns of the first input data. N is less than K/2 and M is greater than K/2.
    Type: Application
    Filed: November 17, 2023
    Publication date: November 7, 2024
    Inventors: Hui HUANG, Chia-Wei YU, Tien-Hung LIN, Jiamei FENG
  • Publication number: 20240371314
    Abstract: The present disclosure related to a common cathode micro led display with a driving circuit, a ground end, a plurality of LED units and a plurality switch units. The driving circuit connected to a plurality of transmission wires. One end of the plurality of LED units or one end of the plurality switch units is electronically connected to the plurality of transmission wires. The ground end is configured with a plurality of scan lines. Free ends formed by the plurality of LED units and the plurality switch units connected in series connect to the scan lines. A plurality of vertical conducted groups or a plurality of horizontal conducted groups are formed according to the switch units. A control unit is configured to drive the plurality of vertical conduction groups or the plurality of horizontal conduction groups. Therefore, the object to avoid voltage drop caused by the drive current is achieved.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 7, 2024
    Applicant: GIANTPLUS TECHNOLOGY CO., LTD.
    Inventor: Wei-Yu CHEN
  • Publication number: 20240371647
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, and a polymer over the die and the molding. The die has a top surface. The molding has a top surface. The polymer has a first bottom surface contact the die and a second surface contacting the molding. The first bottom surface is at a level substantially same as the second bottom surface.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: YU-HSIANG HU, WEI-YU CHEN, HUNG-JUI KUO, WEI-HUNG LIN, MING-DA CHENG, CHUNG-SHI LIU
  • Publication number: 20240371840
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20240371964
    Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
  • Patent number: 12134613
    Abstract: This specification generally relates to an improved method for the manufacture of 3-[(1S)-1-imidazo[1,2-a]pyridin-6-ylethyl]-5-(1-methylpyrazol-4-yl)triazolo[4,5-b]pyrazine (I), or pharmaceutically acceptable salts thereof; polymorphic forms thereof, and intermediates useful in the manufacture of such compounds and salts thereof.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 5, 2024
    Assignees: AstraZeneca AB, Hutchison Medipharma Limited
    Inventors: Andrew Roy Turner, Andrew Timothy Turner, Gareth Paul Howell, Malcolm Allan Young Gall, Keith Raymond Mulholland, Neil Keith Adlington, Zhenping Tian, Bo Liu, Qisun Gong, Wei Yu
  • Patent number: 12135359
    Abstract: A method, an apparatus and a computer device for detecting an open circuit fault are provided. The sample data of the electrical signal at the primary side of the transformer in the CLLLC resonant bidirectional DC/DC converter is performed with spectrum analysis to obtain a first frequency, and whether an open circuit fault occurs in the CLLLC resonant bidirectional DC/DC converter can be determined according to the first frequency and an actual switching frequency.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: November 5, 2024
    Assignee: EAST GROUP CO., LTD.
    Inventors: Wei Yu, Jin Zhao, Shaohui Li
  • Patent number: 12136952
    Abstract: Disclosed are a co-packaged integrated optoelectronic module and a co-packaged optoelectronic switch chip. The co-packaged integrated optoelectronic module includes a carrier board, and an optoelectronic submodule, a slave microprocessor and a master microprocessor disposed on and electrically connected to the carrier board. In the optoelectronic submodule, a digital signal processing chip converts an electrical analog signal into an electrical digital signal, an optoelectronic signal analog conversion chip converts an optical analog signal into the electrical analog signal to the digital signal processing chip, and an optical transceiver chip receives and transmits the optical analog signal to the optoelectronic signal analog conversion chip. The slave microprocessor monitors operation of the optoelectronic submodule.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 5, 2024
    Assignee: DONGGUAN LUXSHARE TECHNOLOGIES CO., LTD
    Inventors: Min-Sheng Kao, ChunFu Wu, Chung-Hsin Fu, QianBing Yan, LinChun Li, Chih-Wei Yu, Chien-Tzu Wu, Yi-Tseng Lin
  • Patent number: D1049726
    Type: Grant
    Filed: July 29, 2024
    Date of Patent: November 5, 2024
    Inventor: Wei Yu
  • Patent number: D1050773
    Type: Grant
    Filed: July 31, 2024
    Date of Patent: November 12, 2024
    Inventor: Wei Yu
  • Patent number: D1051864
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: November 19, 2024
    Assignee: Acer Incorporated
    Inventors: Wei-Yu Lai, Yi-Heng Lee