Patents by Inventor Wen Cheng

Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-focus physiologic sensing device for condensing light
    Patent number: 9980654
    Abstract: A multi-focus physiologic sensing device for condensing light is disclosed, comprises a multi-focus condenser has one first ellipse reflection member, and one second ellipse reflection member is arranged at an end of the first ellipse reflection member. The first ellipse reflection member has a first focus point thereon. The second ellipse reflection member has two second focus points thereon. A boundary between the first ellipse reflection member and the second ellipse reflection member has a first confocal point. Two lighting elements are respectively arranged on the two second focus points to generate light sources, that focus light on the first confocal point through the second ellipse reflection member, and then the detected object reflects the detected light source back to the first confocal point. Then, the detected light source is passes through the sensor from the first focus.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 29, 2018
    Assignee: Automotive Research & Test Center
    Inventors: Shun-Wen Cheng, Chun-Yao Shih, Jih-Tao Hsu
  • MEMS integrated pressure sensor and microphone devices and methods of forming same
    Patent number: 9981841
    Abstract: A micro-electromechanical systems (MEMS) device includes a MEMS substrate having a first opening, a second opening, and a membrane layer comprising a first membrane disposed over the first opening and a second membrane disposed over the second opening. The MEMS device also includes a carrier substrate bonded to a first side of the MEMS substrate, the carrier substrate having a first cavity exposing the first membrane and a second cavity exposing the second membrane, and a cap substrate bonded to a second side of the MEMS substrate. The cap substrate has a third cavity connected to the first opening and a fourth cavity connected to the second opening. The first membrane, the first cavity, and the third cavity are part of a pressure sensor. The fourth cavity extends completely through the cap substrate. The second membrane, the second cavity, and the fourth cavity are part of a microphone.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180146555
    Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first substrate, a second substrate, a drive IC and a protection layer. The first substrate has a first region and a second region. The second substrate is correspondingly disposed on the first region. The drive IC is disposed on the second region. The protection layer is disposed enclosing the drive IC, and the protection layer has a maximum height larger than the height of the drive IC.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 24, 2018
    Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
  • EMBEDDED SOURCE OR DRAIN REGION OF TRANSISTOR WITH DOWNWARD TAPERED REGION UNDER FACET REGION
    Publication number: 20180145173
    Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 24, 2018
    Inventors: CHE-CHENG CHANG, TUNG-WEN CHENG, YUNG JUNG CHANG, ZHE-HAO ZHANG
  • Manufacturing method of semiconductor device with regrown undoped channel and regrown S/D regions
    Patent number: 9978648
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Mu-Tsang Lin
  • Stacked semiconductor structure and method of forming the same
    Patent number: 9975762
    Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Equalization enhancing module, demodulation system and equalization enhancing method
    Patent number: 9979567
    Abstract: An equalization enhancing module includes: a multiplication unit, multiplying a plurality of equalized signals by a scaling coefficient to obtain a plurality of scaled signals; a determination unit, coupled to the multiplication unit, determining whether the plurality of scaled signals are located in a predetermined region to generate a plurality of determination results; a ratio calculating unit, coupled to the determination unit, calculating an inner ratio associated with a ratio of the plurality of scaled signals located in the predetermined region; and a coefficient calculating unit, coupled to the ratio calculating unit, calculating the scaling coefficient according to the inner ratio.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 22, 2018
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chia-Wei Chen, Kai-Wen Cheng, Ko-Yin Lai
  • Backside sensing BioFET with enhanced performance
    Patent number: 9976982
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Yi-Shao Liu, Fei-Lung Lai, Wei-Cheng Lin, Ta-Chuan Liao, Chien-Kuo Yang
  • Method and Structure for CMOS-MEMS Thin Film Encapsulation
    Publication number: 20180118560
    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 3, 2018
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • ERROR LIMITING METHOD, ERROR LIMITER AND DIGITAL RECEIVING CIRCUIT
    Publication number: 20180123735
    Abstract: An error limiting method includes: receiving a first signal and a first error signal, wherein the first error signal is associated with the first signal and a first symbol corresponding to the first signal; calculating a first magnitude value of the first signal; and decreasing an error energy of the first error signal according to the first magnitude value of the first signal to generate a second error signal, and outputting the second error signal to an error feedback circuit.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 3, 2018
    Inventors: CHIA-WEI CHEN, KAI-WEN CHENG, KO-YIN LAI
  • Method and apparatus for reducing fixed pattern noise of image sensor in digital domain
    Patent number: 9961338
    Abstract: A method for reducing fixed pattern noise of an image sensor is provided. The method includes: accessing pixel data of at least one test frame in a test environment; and calculating/deriving average values of each column based on at least one portion of pixel data of the column in the at least one test frame, wherein the average values of columns are used as calibration values for calibrating image pixel data of columns when the image sensor operates in a normal light source environment.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 1, 2018
    Assignee: PixArt Imaging Inc.
    Inventors: Chien-Jung Chou, Mei-Chao Yeh, Wen-Cheng Yen
  • Dust-proof safety hook
    Patent number: 9958002
    Abstract: A dust-proof safety hook contains: a body, a connection shaft, a returning element, a housing sleeve, a resilient element, a rotary sheath, and a positioning bolt. The body includes an accommodation space, an opening, a first segment, and a second segment. The connection shaft includes a first part and a second part, and the returning element is mounted between the body and the connection shaft. The housing sleeve includes a slot which has a limiting portion and two notches. The resilient element is fitted with the connection shaft, and the rotary sheath includes a through orifice and a cut. The positioning bolt is inserted into the through orifice of the rotary sheath and the limiting portion of the slot of the housing sleeve, such that the rotary sheath moves along the slot of the housing sleeve by way of the positioning bolt.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 1, 2018
    Assignee: Win Chance Metal Co., Ltd.
    Inventor: Wen-Cheng Chang
  • Contact resistance control in epitaxial structures of finFET
    Patent number: 9953875
    Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Cheng-Wen Cheng, Chii-Horng Li, Lilly Su, Tuoh Bin Ng
  • Methods and apparatus to manage cache memory in multi-cache environments
    Patent number: 9952999
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage cache memory in multi-cache environments. A disclosed apparatus includes a remote cache manager to identify a remote cache memory communicatively connected to a bus, a delegation manager to constrain the remote cache memory to share data with a host cache memory via the bus, and a lock manager to synchronize the host cache memory and the remote cache memory with a common lock state.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Shiow-Wen Cheng, Robert Joseph Woodruff
  • MEMS device structure with a capping structure
    Patent number: 9938138
    Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity through a via formed into the membrane layer.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Integrated biosensor
    Patent number: 9933388
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a substrate, and a lower metal wire over the substrate and electrically coupled to the sensing device. First and second metal vias are arranged on the lower metal wire at locations set back from sidewalls of the lower metal wire, and first and second upper metal wires respectively cover top surfaces of the first and second metal vias. A dielectric structure surrounds the lower metal wire, the first and second metal vias, and the first and second upper metal wires. A sensing well has sensing surfaces that extend along an upper surface of the lower metal wire and along sidewalls of the first and second metal vias and the first and second upper metal wires.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Chia-Hua Chu, Yi-Hsien Chang, Hsin-Chieh Huang
  • Method of radio resource scheduling in unlicensed spectrum and related apparatuses using the same
    Patent number: 9936393
    Abstract: The disclosure is directed to a method of radio resource scheduling in an unlicensed spectrum and related apparatuses using the same method. In one of the exemplary embodiments, the method would include not limited to transmitting a node control information which may include an occupancy pattern of a radio resource of the unlicensed spectrum before receiving an occupancy notification; transmitting an equipment control information which comprises the occupancy pattern of the radio resource of the unlicensed spectrum before receiving the occupancy notification; transmitting a packet data by using the radio resource of the unlicensed spectrum before receiving the occupancy notification; and receiving the occupancy notification which informs an availability of the radio resource of the unlicensed spectrum.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 3, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Chen Pao, Ching-Wen Cheng, Tzu-Jane Tsai, Yung-Lan Tseng
  • CHAT ROOM MANAGEMENT METHOD, CHAT ROOM SYSTEM AND ELECTRONIC DEVICE AND SERVER THEREOF
    Publication number: 20180091451
    Abstract: The invention provides a chat room management method, a chat room system and an electronic device and a server thereof. The chat room management method includes: establishing a chat group on a chat platform, and establishing multiple sub chat groups in the chat group, wherein the chat group and the sub chat groups of the chat group form a hierarchical chat group structure; recording multiple historical chat records corresponding to the sub chat groups; filtering multiple critical articles from the historical chat records, and sharing the critical articles in the chat group; and logging in to a first sub chat group of the sub chat groups to access the historical chat records of the first sub chat group and the critical articles.
    Type: Application
    Filed: February 9, 2017
    Publication date: March 29, 2018
    Applicant: Elite International Education Services, Inc.
    Inventors: Xue-Ying Gu, Qing-Wen Cheng, Hsing-Chiang Chiang, Su-Jen Liu, Wei-En Kao, Ting-Kang Tsao
  • MEMS DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180086624
    Abstract: A MEMS device includes a substrate, a supporter, a first back plate, a second back plate and a diaphragm. The substrate has a cavity. The supporter is over the substrate. The first back plate is over the cavity and fixed on the supporter. The second back plate is over the cavity and fixed on the supporter. The diaphragm is between the first back plate and the second back plate. The diaphragm includes a first sub-diaphragm and a second sub-diaphragm over the cavity and fixed on the supporter.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 29, 2018
    Inventors: CHUN-WEN CHENG, CHIA-HUA CHU, MING-DAO WU, TZU-HENG WU
  • Method of manufacturing semiconductor device
    Patent number: 9929254
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A portion of the semiconductor fin is protruded from the substrate. The gate stack is disposed over the portion of the semiconductor fin protruded from the substrate. The epitaxy structure is disposed on the substrate and adjacent to the gate stack. The epitaxy structure has a top surface facing away the substrate, and the top surface has at least one curved portion having a radius of curvature ranging from about 5 nm to about 20 nm.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lo, Shih-Hao Chen, Mu-Tsang Lin, Tung-Wen Cheng