Patents by Inventor Wen Cheng

Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180288549
    Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Jung-Huei Peng, Chia-Hua Chu, Chun-wen Cheng, Chin-Yi Cho, Li-Min Hung, Yao-Te Huang
  • Publication number: 20180278260
    Abstract: A bandwidth adjustment method includes obtaining an upper bandwidth limit and a lower bandwidth limit according to an initial upper bandwidth limit and an initial lower bandwidth limit, obtaining an optimum bandwidth according to the upper bandwidth limit and the lower bandwidth limit, and adjusting the initial upper bandwidth limit and the initial lower and width limit according to the optimum bandwidth.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 27, 2018
    Inventors: Ting-Nan CHO, Kai-Wen CHENG, Tai-Lai TUNG
  • Patent number: 10084060
    Abstract: The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Kuo Hui Chang, Che-Cheng Chang, Mu-Tsang Lin
  • Publication number: 20180265351
    Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 10075391
    Abstract: A method for allocating port assignments for transmitting a reserved network stream across a network node comprises determining a cycle time associated with a network node. The method also comprises establishing, for at least one port of the network node, a plurality of virtual layers associated with the cycle time, wherein each of the plurality of virtual layers is divided into 2n equally-spaced slots per cycle (where n>0). The method further comprises receiving a reserved stream request associated with transmission of a reserved stream across the node, and determining a number of slots required to transmit the reserved stream. The method also comprises assigning one or more slots associated with a port of the network node to the transmission of packets associated with the reserved stream based on the determined number of slots. The method further comprises transmitting the stream according to the slot assignment associated with the port of the network node.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 11, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Norman William Finn, Rong Pan, Hiroshi Suzuki, Linda Tin-Wen Cheng, Peter Geoffrey Jones, Hariprasada Rao Ginjpalli, Rudolph Benedict Klecka
  • Patent number: 10074731
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Wei Wang, Chia-Hao Chang, Wen-Cheng Luo
  • Patent number: 10075285
    Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: September 11, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Ting-Nan Cho, Kai-Wen Cheng, Tai-Lai Tung
  • Patent number: 10074680
    Abstract: A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsien Tseng, Nai-Wen Cheng, Shou-Gwo Wuu, Ming-Tsong Wang, Tung-Ting Wu
  • Patent number: 10065852
    Abstract: A MEMS device includes a substrate, a supporter, a first back plate, a second back plate and a diaphragm. The substrate has a cavity. The supporter is over the substrate. The first back plate is over the cavity and fixed on the supporter. The second back plate is over the cavity and fixed on the supporter. The diaphragm is between the first back plate and the second back plate. The diaphragm includes a first sub-diaphragm and a second sub-diaphragm over the cavity and fixed on the supporter.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Ming-Dao Wu, Tzu-Heng Wu
  • Patent number: 10068982
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure also includes a dielectric structure over the semiconductor substrate and adjacent to the gate stack. The dielectric structure is in direct contact with the work function layer and the metal filling.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Mu-Tsang Lin
  • Publication number: 20180238827
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Chun-Wen CHENG, Yi-Shao Liu, Fei-Lung Lai, Wei-Cheng Lin, Ta-Chuan Liao, Chien-Kuo Yang
  • Publication number: 20180240334
    Abstract: The present disclosure illustrates a code activation device used to transmit an activation signal to a back-end device, so as to activate the back-end device. The code activation device comprises a sensing module and a processing module. The sensing module comprises a sensor unit, and the sensor unit generates sensing signals according to a preset action of a trigger object. The processing module connected to the sensing module receives the sensing signals, generates a sensing beat according to interval periods between the sensing signals, and determines whether the sensing beat matches a preset beat, wherein the processing module generates the activation signal when the sensing beat matches the preset beat.
    Type: Application
    Filed: August 29, 2017
    Publication date: August 23, 2018
    Inventors: Yuan-Ping Liu, Chao-Ting Wu, Wei-Ren Lai, Kai-Wen Cheng, Chiao-Yu Hsiao, Wei-Hsun Wang
  • Publication number: 20180231572
    Abstract: The present invention includes methods for the detection of neurotransmission or developmental disorders, including, but not limited to, myasthenia gravis that is seronegative for autoantibodies to the acetylcholine receptor (AChR) and/or muscle specific tyrosine kinase (MuSK), the method including detecting autoantibodies that bind to LRP4, or an epitope thereof. Also included are methods for the treatment of an individual suffering from a neurotransmission disorder, the method including detecting in a bodily fluid of the individual autoantibodies that bind to LRP4, or an epitope thereof, and administering to the patient an effective amount an immunosuppressant and/or another appropriate therapeutic modality. Also included are antibodies that bind to autoantibodies to LRP4 and kits for the detection of neurotransmission or developmental disorders.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 16, 2018
    Applicant: AUGUSTA UNIVERSITY RESEARCH INSTITUTE, INC.
    Inventors: Lin Mei, Wen-Cheng Xiong, Bin Zhang, Chengyong Shen
  • Publication number: 20180233122
    Abstract: A method for performing active noise control upon a target zone includes: using an adaptive filtering circuit to receive at least one microphone signal obtained from a microphone; and, dynamically compensating at least one coefficient of the adaptive filtering circuit to adjust a frequency response of the adaptive filtering circuit according to an energy distribution of the at least one microphone signal, so as to make the adaptive filtering circuit receive the at least one microphone signal to generate a resultant anti-noise signal to the target zone based on the dynamically adjusted frequency response.
    Type: Application
    Filed: July 18, 2017
    Publication date: August 16, 2018
    Inventors: Chao-Ling Hsu, Yiou-Wen Cheng
  • Publication number: 20180226337
    Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 9, 2018
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10043906
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Patent number: 10044949
    Abstract: A digital imaging device including a sensor array, an analog front end and a digital back end. The sensor array is configured to output black pixel data and normal pixel data. The analog front end is configured to amplify the black pixel data and the normal pixel data with a gain, and calibrate the amplified black pixel data and the amplified normal pixel data with a calibration value. The digital back end is configured to digitize the amplified and calibrated black pixel data, calculate a data offset according to digital black pixel data, determine a dynamic adjust scale, calculate the calibration value according to the gain, the data offset and the dynamic adjust scale, and adjust the gain according to the dynamic adjust scale.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 7, 2018
    Assignee: PIXART IMAGING INC.
    Inventors: Chien-Jung Chou, Han-Chi Liu, Wen-Cheng Yen
  • Publication number: 20180220361
    Abstract: A method of system information transmission for a network in a wireless communication system is disclosed. The method comprises broadcasting essential minimum system information (SI) of a cell of the wireless communication system with fixed scheduled on a downlink broadcast channel, wherein the essential minimum SI includes scheduling information for non-essential minimum SI of at least one of the cell and an auxiliary cell or a frequency location, the non-essential minimum SI is broadcasted with dynamically scheduled on a downlink shared channel, and the scheduling information includes a time and frequency resource configuration and an availability information for indicating whether the cell broadcasts the non-essential minimum SI.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 2, 2018
    Inventors: Ching-Wen Cheng, Hung-Chen Chen
  • Publication number: 20180220259
    Abstract: A location identification device, adopted in an audio output device outputting an audio signal, includes a first audio receiving device, a second audio receiving device, and a processor. The first audio receiving device samples the audio signal by a sampling frequency to generate first sample points. A waveform of the audio signal is a superposition result of a high frequency signal and an envelope. The second audio receiving device, which is away from the first audio receiving device at a predetermined distance, samples the audio signal by the sampling frequency to generate second sample points. The processor obtains the first envelope of a first characteristic value and the second envelope of a second characteristic value for identifying a location of the audio output device according to a time difference and an amplitude difference between the first characteristic value and the second characteristic value.
    Type: Application
    Filed: March 20, 2018
    Publication date: August 2, 2018
    Inventors: Po-Jen Tu, Jia-Ren Chang, Ming-Chun Fang, Chun-Chi Ho, Chia-Hsun Lee, Wen-Cheng Hsu, Chao-Kuang Yang
  • Publication number: 20180214426
    Abstract: The present invention provides novel pyrazolo[4,3-c]quinoline derivatives exhibiting specifically inhibition activity to microbiota ?-glucuronidase, whereby providing potent activities to prevent chemotherapy-induced diarrhea (CID) of cancers. Therefore, the compounds of the present invention can be used as (1) chemotherapy-adjuvant to prevent chemotherapy-induced diarrhea (CID) and enhance chemotherapeutic efficiency of cancers; (2) health-food supplement to prevent the carcinogens induced colon carcinoma.
    Type: Application
    Filed: May 26, 2016
    Publication date: August 2, 2018
    Inventors: Yeh-Long Chen, Tian-Lu Cheng, Cherng-Chyi Tzeng, Chih-Hua Tseng, Ta-Chun Cheng, Kai-Wen Cheng, Wei-Fen Luo