Patents by Inventor Wen Cheng

Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180327254
    Abstract: A method embodiment includes providing a MEMS wafer. A portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer. The carrier wafer is etched to expose the first membrane and a first surface of the second membrane to an ambient environment. A MEMS structure is formed in the MEMS wafer. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device. The cap wafer comprises an interconnect structure. A through-via electrically connected to the interconnect structure is formed in the cap wafer.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 15, 2018
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 10121698
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Patent number: 10121820
    Abstract: A method of processing an image sensor system, comprising steps of placing a first cover member on top of an image sensor; coating the image sensor and the first cover member with a dark coating agent; removing the first cover member from the image sensor; placing a second cover member on top of the image sensor; affixing the image sensor on to a permanent mount to form an electrical coupling between the image sensor and the permanent mount; removing the second cover member from the image sensor; wherein the first cover member completely covers a top portion of the image sensor; and wherein the second cover member includes an internal rib configured to form a contact seal with the image sensor.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 6, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Teng-Sheng Chen, Yuan-Wen Cheng, Chia-Yang Chang, Yi Qin, Wen-Jian Xia
  • Patent number: 10123147
    Abstract: Methods and apparatuses pertaining to enhanced audio effect realization for virtual reality may involve receiving data in a virtual reality setting. The data may be related to audio samples from one or more sound sources, motions of the one or more sound sources, and motions of a user. Physics simulation may be performed for realization of one or more audio effects based on the received data. Signal processing may be performed using a result of the physics simulation. Audio outputs may be provided using a result of the signal processing.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 6, 2018
    Assignee: MEDIATEK INC.
    Inventors: Xin-Wei Shih, Yiou-Wen Cheng
  • Publication number: 20180315660
    Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.
    Type: Application
    Filed: April 23, 2018
    Publication date: November 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wen CHENG, Chii-Horng Li, Lilly Su, Tuoh Bin Ng
  • Publication number: 20180313783
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 1, 2018
    Inventors: Chun-Wen CHENG, Yi-Shao LIU, Fei-Lung LAI
  • Publication number: 20180309943
    Abstract: A digital imaging device including a sensor array, an analog front end and a digital back end. The sensor array is configured to output black pixel data and normal pixel data. The analog front end is configured to amplify the black pixel data and the normal pixel data with a gain, and calibrate the amplified black pixel data and the amplified normal pixel data with a calibration value. The digital back end is configured to digitize the amplified and calibrated black pixel data, calculate a data offset according to digital black pixel data, determine a dynamic adjust scale, calculate the calibration value according to the gain, the data offset and the dynamic adjust scale, and adjust the gain according to the dynamic adjust scale.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: CHIEN-JUNG CHOU, Han-Chi Liu, Wen-Cheng Yen
  • Publication number: 20180310014
    Abstract: A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.
    Type: Application
    Filed: December 14, 2017
    Publication date: October 25, 2018
    Inventors: KUAN-CHOU LEE, KAI-WEN CHENG, TAI-LAI TUNG
  • Publication number: 20180305201
    Abstract: A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Publication number: 20180309274
    Abstract: A combination cable mounting fixture structure is disclosed. The structure includes plural cable units that can be distinguished as first cable units, second cable units, and third cable units. The first cable unit can be selected to be fixed to a flat surface, each of the cable units is provided with at least one male head connecting portion, at least one female head connecting portion, or is provided with both a male head connecting portion and a female head connecting portion. The female (male) head connecting portion of the second cable unit is connected to the adjacent male (female) head connecting portion, and the female (male) head connecting portion of the third cable unit is connected to the adjacent male (female) head connecting portion.
    Type: Application
    Filed: October 10, 2017
    Publication date: October 25, 2018
    Inventors: Wen-Cheng Liu, Jerric Paul
  • Patent number: 10111162
    Abstract: The present disclosure is directed to a method of controlling network traffic for a user equipment (UE) and a base station (BS). In one of the exemplary embodiments, the disclosure is directed to a method of controlling network traffic for a UE. The method would include not limited to determining whether to select a target access network, and transmitting a traffic re-direct inform message in response to the selection of the target access network, wherein the traffic re-direct inform message comprises information of the target access network and a traffic flow indicator corresponding to at least one traffic flow.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: October 23, 2018
    Assignee: Acer Incorporated
    Inventors: Hung-Chen Chen, Ching-Wen Cheng
  • Patent number: 10109741
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10101616
    Abstract: A pixel matrix includes pixel units. The pixel units are arranged in a repeating pattern, in which each of the pixel units includes transparent pixels, reflective pixels, and switch components. Each of the transparent pixels includes a transparent electrode and a transparent color resist layer disposed on the transparent electrode. Each of the reflective pixels includes a reflective electrode. The switch components are connected to the transparent electrodes of the transparent pixels and the reflective electrodes of the reflective pixels respectively for driving the transparent pixels and the reflective pixels individually.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 16, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hui Chu Ke, Sheng-Wen Cheng
  • Patent number: 10103078
    Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Chang, Cheng-Yuan Tsai, Kai-Wen Cheng
  • Patent number: 10101292
    Abstract: A micro-electro mechanical system (MEMS) humidity sensor includes a first substrate, a second substrate and a sensing structure. The second substrate is substantially parallel to the first substrate. The sensing structure is between the first substrate and the second substrate, and bonded to a portion of the first substrate and a portion of the second substrate, in which the second substrate includes a conductive layer facing the sensing structure, and a first space between the first substrate and the sensing structure is communicated with or isolated from outside, and a second space between the conductive layer and the sensing structure is communicated with an atmosphere, and the sensing structure, the second space and the conductive layer constitute a capacitor configured to measure permittivity of the atmosphere, and humidity of the atmosphere is derived from the permittivity of the atmosphere, pressure of the atmosphere and temperature.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Tsun Chen, Chia-Hua Chu, Jui-Cheng Huang, Chun-Wen Cheng, Cheng-Hsiang Hsieh
  • Publication number: 20180294947
    Abstract: A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.
    Type: Application
    Filed: August 30, 2017
    Publication date: October 11, 2018
    Inventors: Ting-Nan CHO, Kai-Wen CHENG, Tai-Lai TUNG
  • Publication number: 20180292927
    Abstract: A touch electrode array disposed on a substrate and including at least one first sensing electrode and at least one protective electrode is provided. The first sensing electrode is formed by a network structure. The network structure includes a solid portion and at least one opening portion defined by the solid portion. The at least one protective electrode overlaps with the at least one opening potion in one direction. Moreover, a touch display apparatus including the touch electrode array is also provided.
    Type: Application
    Filed: July 4, 2017
    Publication date: October 11, 2018
    Applicant: Au Optronics Corporation
    Inventors: Yu-Chin Chu, Sheng-Wen Cheng
  • Patent number: 10094801
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. An amplification factor of the BioFET device may be provided by a difference in capacitances associated with the gate structure on the first surface and with the interface layer formed on the second surface.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Yi-Shao Liu, Rashid Bashir, Fei-Lung Lai, Chun-wen Cheng
  • Patent number: 10096767
    Abstract: A Magnetoresistive Tunnel Junction (MTJ) device includes an elongated MTJ structure formed onto a substrate, the MTJ structure including a magnetic reference layer and a tunnel barrier layer. The MTJ device also includes a number of discrete free magnetic regions disposed onto the tunnel barrier layer. The ratio of length to width of the elongated MTJ structure is such that the magnetic field of the magnetic reference layer is pinned in a single direction.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chwen Yu, Kai-Wen Cheng, Tien-Wei Chiang, Dong Cheng Chen
  • Patent number: D832217
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 30, 2018
    Assignee: MIEZO INC.
    Inventors: Wei-Ren Lai, Wei-Hsun Wang, Chao-Ting Wu, Yuan-Ping Liu, Kai-Wen Cheng, Chiao-Yu Hsiao