Abstract: A semiconductor structure includes a substrate including a plurality of vias passing through the substrate and filled with a conductive or semiconductive material, and an oxide layer surrounding the conductive or semiconductive material, the substrate defining a cavity therein; a membrane disposed over the substrate and the cavity; a heater disposed within the membrane and electrically connected with the substrate; and a sensing electrode disposed over the membrane and the heater.

Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

Abstract: A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Abstract: A structure and a fabrication method thereof are provided. The method includes the following operations. A device substrate having a first surface and a second surface opposite to each other is received. A carrier substrate having a third surface and a fourth surface opposite to each other is received. An intermediate layer is formed between the third surface of the carrier substrate and the second surface of the device substrate. The second surface of the device substrate is attached to the third surface of the carrier substrate. The device substrate is thinned from the first surface. A device is formed over the first surface of the device substrate. The carrier substrate and the device substrate are patterned from the fourth surface to form a cavity in the carrier substrate, the intermediate layer and the device substrate.

Abstract: An analog-to-digital module includes a sampling unit, for generating an output voltage between a positive output end and a negative output end according to a positive input voltage of a positive input end and a negative input voltage of a negative input end; a comparing unit, for generating a digital output signal according to magnitude relationship between the output voltage and a reference voltage; a variable current source, for generating a variable current according to the digital output signal at the negative input end in a first period according to a control signal; a measured current source, for generating a measured current at the negative input end; and an adjusting unit, for adjusting the output voltage according to the digital output signal in a second period according to the control signal; wherein the first period does not overlap the second period.

Abstract: A flame simulating device includes an upper part, a light source, a container and an oscillation device. The upper part has a flame element which freely swings relative to the upper part, and the light source located in the upper part emits light toward the flame-shaped portion. The container is located below the upper part and contains liquid therein. The oscillation device is located at the underside of the container and oscillates the liquid in the container to generate liquid vapor and liquid droplets, the liquid droplets hit and irregularly swing the flame element. The liquid vapor provides a foggy environment.

Abstract: Disclosed are a method and a system of device-to-device tunnel establishment between small cells, applied to a wireless backhaul management device, a first small cell and a second small cell. The method comprises: matching the first small cell and the second small cell according to a first discovery response and a second discovery response; submitting a match report; replying with a match report response; conducting a D2D connection authentication procedure between the second small cell and the first small cell; wirelessly connecting the second small cell and the first small cell, conducting a connection test and submitting a connection test report; replying with a D2D tunnel establishment decision according to the connection test report; and establishing a D2D tunnel between the second small cell and the first small cell.

Abstract: The present disclosure provides a biosensor device wafer testing and processing methods, system and apparatus. The biosensor device wafer includes device areas separated by scribe lines. A number of test areas that allow fluidic electrical testing are embedded in scribe lines or in device areas. An integrated electro-microfluidic probe card includes a fluidic mount that may be transparent, a microfluidic channels in the fluidic mount in a testing portion, at least one microfluidic probe and a number of electronic probe tips at the bottom of the fluidic mount, fluidic and electronic input and output ports on the sides of the fluidic mount, and at least one handle lug on the fluidic mount. The method includes aligning a wafer, mounting the integrated electro-microfluidic probe card, flowing one or more test fluids in series, and measuring and analyzing electrical properties to determine process qualities and an acceptance level of the wafer.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate.

Abstract: Some embodiments of the present disclosure provide a gas sensor in an IOT. The gas sensor includes a substrate, a conductor disposed above the substrate, and a sensing film disposed over the conductor. The conductor has a top-view pattern including a plurality of openings, a minimal dimension of the opening being less than about 4 micrometer; and a perimeter enclosing the opening. Some embodiments of the present disclosure provide a method of manufacturing a gas sensor. The method includes receiving a substrate; forming a conductor, over the substrate; patterning the conductor to form a plurality of openings in the conductor by an etching operation, and forming a gas-sensing film over the conductor. The openings are arranged in a repeating pattern, and a minimal dimension of the opening being about 4 micrometer.

Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate and a MEMS substrate bonded with the CMOS substrate. The CMOS substrate includes a semiconductor substrate, a first dielectric layer formed over the semiconductor substrate, and a plurality of conductive pads formed in the first dielectric layer. The MEMS substrate includes a semiconductor layer having a movable element and a second dielectric layer formed between the semiconductor layer and the CMOS substrate. The MEMS substrate also includes a closed chamber surrounding the movable element. The MEMS substrate further includes a blocking layer formed between the closed chamber and the first dielectric layer of the CMOS substrate. The blocking layer is configured to block gas, coming from the first dielectric layer, from entering the closed chamber.

Abstract: A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

Abstract: A method of forming a semiconductor device comprises bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a plurality of chip package portions. The capping wafer comprises a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is configured to substantially align with a corresponding chip package portion of the plurality of chip package portions. The method also comprises separating the wafer package into a plurality of chip packages. Each chip package of the plurality of chip packages comprises at least one chip package portion of the plurality of chip package portions.

Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.

Abstract: A nail gun includes a body, a valve unit, a nail striking member and a detector. The body has a nail path, an air chamber, and an intake chamber guiding flow of air into the air chamber. The nail striking member is drivable by air pressure in the air chamber for striking a nail in the nail path. The valve unit is operable to switch between unblocking and blocking states to respectively permit and prevent fluid communication between the intake chamber and the air chamber. The detector is connected pivotally to the body, and is contactable with the valve unit such that, when there is no nail in the nail path, the valve unit is controlled by the detector to be in the blocking state.