Abstract: A semiconductor structure includes a first device, a second device, a first hole, a second hole, and a sealing object. The second device is contacted to the first device, wherein a chamber is formed between the first device and the second device. The first hole is disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference. The second hole is disposed in the second device and aligned to the first hole. The sealing object seals the second hole. The first end links with the chamber, and the first circumference is different from the second circumference.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes a first substrate, a plurality of vias passing through the first substrate and filled with a conductive or semiconductive material and a first oxide layer surrounding the conductive or semiconductive material, a cavity surrounded by the first substrate, a metallic material disposed over the first surface, a second oxide layer disposed over the second surface, a membrane disposed over the second oxide layer and the cavity, a heater disposed within the membrane, a sensing electrode disposed over the membrane and the heater, and a sensing material disposed over the cavity and contacting with the sensing electrode. The second device includes a second substrate, and a bonding structure disposed over the second substrate. The metallic material is bonded with the bonding structure to integrate the first device with the second device.

Abstract: A micro-electro mechanical system (MEMS) device is provided. The MEMS device includes a cap substrate and a MEMS substrate bonded with the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first closed chamber between the MEMS substrate and the cap substrate, and the first movable element is in the first closed chamber. The MEMS device further includes an outgassing layer in the first closed chamber. In addition, the MEMS device includes a second closed chamber between the MEMS substrate and the cap substrate, and the second movable element is in the second closed chamber.

Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package having two MEMS devices with different pressures, and an associated method of formation. In some embodiments, the (MEMS) package includes a device substrate and a cap substrate bonded together. The bonded substrate comprises a first cavity corresponding to a first MEMS device having a first pressure and a second cavity corresponding to a second MEMS device having a different second pressure. The second cavity comprises a major volume and a vent hole connected by a lateral channel disposed between the device substrate and the cap substrate and the vent hole is hermetically sealed by a sealing structure.

Abstract: A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer.

Abstract: A power supply device adapted to being coupled to an electronic apparatus through an input interface is provided. The power supply device includes a first-polarity voltage line, a second-polarity voltage line, and an output interface. The first-polarity voltage line and the second-polarity voltage line are disconnected with each other. The output interface is configured to supply a power to the electronic apparatus through the input interface. When the output interface is externally approached or forced by the input interface, the output interface chooses one of the first-polarity voltage line and the second-polarity voltage line as a chosen voltage line for the power. Multiple power supply devices may be arranged to be a power supply system.

Abstract: A method for forming a micro-electro mechanical system (MEMS) device is provided. The method includes bonding a semiconductor substrate with a carrier substrate through a dielectric layer and patterning the semiconductor substrate into multiple elements. The method also includes partially removing the dielectric layer to release some of the elements such that the released elements become one (or more) first movable element and one (or more) second movable element. The method further includes bonding a cap substrate with the semiconductor substrate to form a first closed chamber containing the first movable element and a second closed chamber containing the second movable element. In addition, the method includes opening the second closed chamber and sealing the second closed chamber after vacuumizing the second closed chamber such that the second closed chamber has a reduced pressure smaller than that of the first closed chamber.

Abstract: An electrical connector connecting with a cable electrically includes a mating member, a printed circuit board connected with the mating member and the cable electrically, a light source positioned on the printed circuit board, a detector controlling the light source, a light transmissive member permitting transmission of a light emitted from the light source therethrough, a metal shell enclosing the light transmissive member and the printed circuit board, and a detective member connecting the detector and the metal shell electrically.

Abstract: A sensor assembly is provided for a portable electronic device. The sensor assembly includes a proximity sensor and a module including shielding. The proximity sensor is connected to the shielding such that the shielding selectively functions as a sensor electrode for the proximity sensor.

Abstract: A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0?D1?D2 (but D1 and D2 are not zero at the same time).

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A portion of the semiconductor fin is protruded from the substrate. The gate stack is disposed over the portion of the semiconductor fin protruded from the substrate. The epitaxy structure is disposed on the substrate and adjacent to the gate stack. The epitaxy structure has a top surface facing away the substrate, and the top surface has at least one curved portion having a radius of curvature ranging from about 5 nm to about 20 nm.

Abstract: An active noise control system and associated auto-selection method for modeling a secondary path for the active noise control system are provided. The method includes the steps of: receiving a reference signal; filtering the reference signal with a secondary-path estimation filter to obtain a filtered reference signal, wherein the secondary path estimation filter is determined from a plurality of candidate secondary-path estimation filters; filtering the reference signal with an adaptive filter to provide a compensation signal; sensing a residual noise signal at a listening position of the active noise control system; and adapting filter coefficients of the adaptive filter according to the residual noise signal and the filtered reference signal.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid.

Abstract: An embodiment includes a low-latency mechanism for performing a checkpoint on a distributed application. More specifically, an embodiment of the invention includes processing a first application on a compute node, which is included in a cluster, to produce first computed data and then storing the first computed data in volatile memory included locally in the compute node; halting the processing of the first application, based on an initiated checkpoint, and storing first state data corresponding to the halted first application in the volatile memory; storing the first state information and the first computed data in non-volatile memory included locally in the compute node; and resuming processing of the halted first application and then continuing the processing the first application to produce second computed data while simultaneously pulling the first state information and the first computed data from the non-volatile memory to an input/output (IO) node.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: A method for reducing fixed pattern noise of an image sensor is provided. The method includes: accessing pixel data of at least one test frame in a test environment; and calculating/deriving average values of each column based on at least one portion of pixel data of the column in the at least one test frame, wherein the average values of columns are used as calibration values for calibrating image pixel data of columns when the image sensor operates in a normal light source environment.

Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device. In an embodiment, a device includes a substrate; a MEMS structure disposed above a sacrificial layer opening above the substrate; a release aperture disposed at substantially a same level above the sacrificial layer opening as the MEMS structure; a first cap over the MEMS structure and the sacrificial layer opening, a leg of the first cap disposed between the MEMS structure and the release aperture; and a second cap plugging the release aperture.

Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a substrate, and a lower metal wire over the substrate and electrically coupled to the sensing device. First and second metal vias are arranged on the lower metal wire at locations set back from sidewalls of the lower metal wire, and first and second upper metal wires respectively cover top surfaces of the first and second metal vias. A dielectric structure surrounds the lower metal wire, the first and second metal vias, and the first and second upper metal wires. A sensing well has sensing surfaces that extend along an upper surface of the lower metal wire and along sidewalls of the first and second metal vias and the first and second upper metal wires.