Patents by Inventor Wen Cheng

Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9617147
    Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Jiou-Kang Lee, Kai-Chih Liang, Chung-Hsien Lin, Te-Hao Lee
  • Publication number: 20170098698
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A portion of the semiconductor fin is protruded from the substrate. The gate stack is disposed over the portion of the semiconductor fin protruded from the substrate. The epitaxy structure is disposed on the substrate and adjacent to the gate stack. The epitaxy structure has a top surface facing away the substrate, and the top surface has at least one curved portion having a radius of curvature ranging from about 5 nm to about 20 nm.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang LO, Shih-Hao CHEN, Mu-Tsang LIN, Tung-Wen CHENG
  • Patent number: 9611141
    Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Publication number: 20170090522
    Abstract: A portable electronic device includes a first body and a second body. The first body includes a casing, a supporter, a first magnetic component and a torsion component. The casing includes an accommodating trench and a first trench communicated with the accommodating trench. A first lateral of the supporter is pivoted to the casing via the torsion component, and a second lateral of the supporter includes a notch. The magnetic component is slidably disposed in the first trench. The second body is pivoted to the first body and includes a second magnetic component. When the supporter is located in the accommodating trench and the first magnetic component extends into the notch, the supporter is positioned inside the accommodating trench by the first magnetic component, and the torsion component stores elastic potential energy.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Shun Lu, Ming-Chung Liu, Kun-Hsin Liu, Yun Bai, Yu-Wen Cheng
  • Publication number: 20170090234
    Abstract: A pixel matrix includes pixel units. The pixel units are arranged in a repeating pattern, in which each of the pixel units includes transparent pixels, reflective pixels, and switch components. Each of the transparent pixels includes a transparent electrode and a transparent color resist layer disposed on the transparent electrode. Each of the reflective pixels includes a reflective electrode. The switch components are connected to the transparent electrodes of the transparent pixels and the reflective electrodes of the reflective pixels respectively for driving the transparent pixels and the reflective pixels individually.
    Type: Application
    Filed: December 7, 2016
    Publication date: March 30, 2017
    Inventors: Hui CHU KE, Sheng-Wen Cheng
  • Patent number: 9604843
    Abstract: Embodiments of the present disclosure include MEMS devices and methods for forming MEMS devices. An embodiment is a method for forming a microelectromechanical system (MEMS) device, the method including forming a MEMS wafer having a first cavity, the first cavity having a first pressure, and bonding a carrier wafer to a first side of the MEMS wafer, the bonding forming a second cavity, the second cavity having a second pressure, the second pressure being greater than the first pressure. The method further includes bonding a cap wafer to a second side of the MEMS wafer, the second side being opposite the first side, the bonding forming a third cavity, the third cavity having a third pressure, the third pressure being greater than the first pressure and less than the second pressure.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 9604840
    Abstract: A device includes a stationary structure, a spring and a proof mass. The stationary structure has a first portion and a second portion. The spring is over a substrate. The spring has a first protrusion protruded from an edge and extended toward the first portion of the stationary structure. The proof mass is over the substrate and supported by the sparing. The proof mass has a second protrusion protruded from an edge and extended toward the second portion of the stationary structure. A first gap between the first protrusion and the first portion is less than a second gap between the second protrusion and the second portion.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMAPNY LTD.
    Inventors: Chun-Wen Cheng, Jiou-Kang Lee
  • Publication number: 20170081173
    Abstract: The present disclosure provides a CMOS MEMS device. The CMOS MEMS device includes a first substrate, a second substrate, a first polysilicon and a second polysilicon. The second substrate includes a movable part and is located over the first substrate. The first polysilicon penetrates the second substrate and is adjacent to a first side of the movable part of the second substrate. The second polysilicon penetrates the second substrate and is adjacent to a second side of the movable part of the second substrate.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: YU-CHIA LIU, CHIA-HUA CHU, CHUN-WEN CHENG
  • Patent number: 9599870
    Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: March 21, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Gang-Yi Lin, Ya-Ling Hsu, Yu-Ching Wu, Hao-Wen Cheng, Chen-Hsien Liao, Wen-Hao Hsu, Pei-Chun Liao, Tien-Lun Ting, Jenn-Jia Su
  • Publication number: 20170077302
    Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: Tung-Wen Cheng, Che-Cheng Chang, Mu-Tsang Lin, Bo-Feng Young, Cheng-Yen Yu
  • Publication number: 20170076946
    Abstract: A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Inventors: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Chun-Lung Ni, Jr-Jung Lin, Chih-Han Lin
  • Publication number: 20170070939
    Abstract: A system including a constellation of satellites in Low Earth Orbit and a plurality of ground stations to enable continuous communication for other geocentric, non-geosynchronous spacecraft. Network latency, Doppler effects, and router handover time are minimized through selection of orbital parameters for the satellite constellation and locations of ground stations. A plurality of polar or near polar orbit planes is presented at equally spaced right ascension of the ascending node (RAAN), in an alternative ascending-descending pattern. Inter-satellite communication is performed in-plane to relay data to a ground station, and out-of-plane or in-plane to communicate with another satellite that is not a member of the constellation. The number and location of ground stations is selected based on the number of small satellites and orbital planes in order to maintain continuous communications.
    Type: Application
    Filed: September 7, 2016
    Publication date: March 9, 2017
    Inventors: Wen Cheng CHONG, MIna MITRY
  • Publication number: 20170065958
    Abstract: The present disclosure relates to a method of depositing a fluid onto a substrate. In some embodiments, the method may be performed by mounting a substrate to a micro-fluidic probe card, so that the substrate abuts a cavity within the micro-fluidic probe card that is in communication with a fluid inlet and a fluid outlet. A first fluidic chemical is selectively introduced into the cavity via the fluid inlet of the micro-fluidic probe card.
    Type: Application
    Filed: November 18, 2016
    Publication date: March 9, 2017
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Yi-Shao Liu, Fei-Lung Lai, Shang-Ying Tsai
  • Publication number: 20170066646
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a first substrate, a plurality of vias passing through the first substrate and filled with a conductive or semiconductive material and a first oxide layer surrounding the conductive or semiconductive material, a cavity surrounded by the first substrate, a metallic material disposed over the first surface, a second oxide layer disposed over the second surface, a membrane disposed over the second oxide layer and the cavity, a heater disposed within the membrane, a sensing electrode disposed over the membrane and the heater, and a sensing material disposed over the cavity and contacting with the sensing electrode. The second device includes a second substrate, and a bonding structure disposed over the second substrate. The metallic material is bonded with the bonding structure to integrate the first device with the second device.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 9, 2017
    Inventors: CHUN-WEN CHENG, CHIA-HUA CHU, FEI-LUNG LAI, SHIANG-CHI LIN
  • Publication number: 20170057814
    Abstract: The present disclosure relates an integrated chip having one or more MEMS devices. In some embodiments, the integrated chip has a carrier substrate with one or more cavities disposed within a first side of the carrier substrate. A dielectric layer is disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate. The dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities. A bonding structure, including an intermetallic compound having a plurality of metallic elements, abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate.
    Type: Application
    Filed: June 1, 2016
    Publication date: March 2, 2017
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Jung-Huei Peng
  • Publication number: 20170059515
    Abstract: A method for testing a partially fabricated bio-sensor device wafer includes aligning the partially fabricated bio-sensor device wafer on a wafer stage of a wafer-level bio-sensor processing tool. The method further includes mounting an integrated electro-microfluidic probe card to a device area on the partially fabricated bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface. The method further includes electrically connecting one or more electronic probe tips disposed on the first major surface of the integrated electro-microfluidic probe card to conductive areas of the device area. The method further includes flowing a test fluid from a fluid supply to the integrated electro-microfluidic probe card. The method further includes electrically measuring via the one or more electronic probe tips a first electrical property of one or more bio-FETs of the device area based on the test fluid flow.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Inventors: Yi-Shao LIU, Fei-Lung LAI, Chun-Ren CHENG, Chun-Wen CHENG
  • Publication number: 20170054655
    Abstract: A method for allocating port assignments for transmitting a reserved network stream across a network node comprises determining a cycle time associated with a network node. The method also comprises establishing, for at least one port of the network node, a plurality of virtual layers associated with the cycle time, wherein each of the plurality of virtual layers is divided into 2n equally-spaced slots per cycle (where n>0). The method further comprises receiving a reserved stream request associated with transmission of a reserved stream across the node, and determining a number of slots required to transmit the reserved stream. The method also comprises assigning one or more slots associated with a port of the network node to the transmission of packets associated with the reserved stream based on the determined number of slots. The method further comprises transmitting the stream according to the slot assignment associated with the port of the network node.
    Type: Application
    Filed: August 26, 2016
    Publication date: February 23, 2017
    Inventors: Norman William Finn, Rong Pan, Hiroshi Suzuki, Linda Tin-Wen Cheng, Peter Geoffrey Jones, Hariprasada Rao Ginjpalli, Rudolph Benedict Klecka
  • Patent number: 9573806
    Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 9577191
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
  • Publication number: 20170044004
    Abstract: Some embodiments of the present disclosure provide a microelectromechanical systems (MEMS). The MEMS includes a semiconductive block. The semiconductive block includes a protruding structure. The protruding structure includes a bottom surface. The semiconductive block includes a sensing structure. A semiconductive substrate includes a conductive region. The conductive region includes a first surface under the sensing structure. The first surface is substantially coplanar with the bottom surface. A dielectric region includes a second surface not disposed over the first surface.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 16, 2017
    Inventors: CHUN-WEN CHENG, JUNG-HUEI PENG, CHIA-HUA CHU, NIEN-TSUNG TSAI, YAO-TE HUANG, LI-MIN HUNG, YU-CHIA LIU