Abstract: An amplifier includes a subtracting unit for generating an error signal according to an input signal and an output signal; a noise shaping unit for executing a noise shaping operation on the error signal to produce a noise-shaped signal; a pulse adjustment unit for generating a control signal according to the noise-shaped signal and the input signal; and a power stage for generating the output signal according to the control signal.

Abstract: In prior arts, additional pulse-width modulators and more costs are needed for increasing the current output. The invention provides a synchronized parallel running power converter. The power converter includes multiple power converters controlled by single-phase or double-phase pulse-width modulators. Each power converter includes a first pulse input port, a second pulse input port and a current output port. Each first pulse input ports are coupled, and each second pulse input ports are coupled also, so that each power converter is controlled by the same pulse signal and provide a same output current to be added as several times of current output.

Abstract: A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSTN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Abstract: The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.

Abstract: An image display device and a method thereof are proposed to solve the problem of bad image processing performance of existent image display devices. The image display device comprises an image processing controller, a transmission interface for input of an image signal, a plurality of graphics processing unit for graphics acceleration, an image memory for storing the image signal, and a video signal generating module for providing a video signal to a display device. The graphics processing units respectively process the image signal in the image memory so that the image processing controller can control the video signal generating module to perform image modulation to the image signal according to the operation results of the graphics processing units. The video signal generating module then generates a video signal for output. Through these graphics processing units, the whole performance can be enhanced.

Abstract: A microcontroller device for extending memory address space by inserting a waiting state and an operation method on the device. The device includes a CPU, a ROM, and a memory interface controller. In the device, the memory interface controller inserts a waiting state into the CPU when address of the information or the program to be fetched by the CPU is not located within a predetermined address range until the information or the program is completely fetched.

Abstract: A planar light source including a transflective film, a plurality of cold cathode fluorescence flat lamps and at least one reflective component to provide a uniform light source is described. A portion of the light emitted from the emitting areas of the cold cathode fluorescence flat lamps passes through the transflective film, and the other portion of the light is reflected to the reflective component by the transflective film. Then, the light is reflected to the dark areas between the emitting areas to compensate the brightness of the dark areas. When the brightness of the dark areas is compensated, the planar light source provides a uniform light without dark stripes.

Abstract: An art of applying microbes to the treatment of a fluid is provided. The feature is that a large mass of microbe carriers are distributed to a plurality of containers each including a restriction structure and a fluid passage structure, wherein the restriction structure restricts the moving of the microbe carrier so that the microbe carrier is either stationary or movable in a restricted region, and the fluid passage structure provides the fluid with a flow passage between the interior and the exterior of the container so that the microbe carrier in the container contacts the fluid. Various applications based on the containers or the like are also disclosed.

Abstract: A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

Abstract: The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: A self-watering breeding device has a culturing slide, a capillary sheet, and an optional immersion sheet. The culturing slide has a gradual slope, a steep slope and a guiding arc connected between the gradual slope and the steep slope. The gradual slope has multiple through holes to allow roots of seeds extending through the through holes. The capillary sheet attaches on the steep slope and extends over the guiding arc. The immersion sheet attaches on the gradual slope and partially overlaps with the capillary sheet. When the culturing slide stands on a basin full of water, the capillary sheet absorbs water and guides water over the guiding arc to reach the gradual slope. Then, water travels over the entirely immersion sheet to supply seeds on the gradual slope by gravity attraction. Additionally, exceeded water slides along the gradual slope to the basin to recycle.

Abstract: A circuit capable of updating the power supply specification of microprocessor and a method thereof are proposed. The circuit is disposed on a computer motherboard, and makes use of downloaded program data of the power supply specification of a new microprocessor a microprocessor is updated. The circuit uses a programmable memory IC to execute the program data of the power supply specification for automatically updating and modifying the required power supply specification of the microprocessor. Through a PWM control unit, a drive unit and a power switch, the required power supply specification of a new microprocessor can be provided for the microprocessor to perform boot actions.

Abstract: A system for heating a load-lock chamber, particularly that of a plasma etching system for etching semiconductor wafer substrates. The load-lock chamber heating system includes a heater that is provided in fluid communication with a gas supply which contains an inert gas such as nitrogen. A gas pump pumps the gas from the gas supply through the heater, and from the heater into the load-lock chamber. The gas heats the load-lock chamber to prevent or minimize condensation of corrosive etching gases onto the interior surfaces of the load-lock chamber as well as the surfaces of substrates contained therein.

Abstract: A self-watering breeding device has a culturing slide (10), a capillary sheet (20), and an optional immersion sheet (22). The culturing slide (10) has a gradual slop (11), a steep slop (12) and a guiding arc (122) connected between the gradual slop (11) and the steep slop (12). The capillary sheet (20) attaches on the steep slop (12) and extends over the guiding arc (122). The immersion sheet (22) attaches on the gradual slop (11) and partially overlaps with the capillary sheet (20). When the culturing slide (10) stands on a basin full of water, the capillary sheet (20) absorbs water and guides water over the guiding arc (122) to reach the gradual slop (11). Then, water travels over the entirely immersion sheet (22) to supply seeds on the gradual slop (11) by gravity attraction. Additionally, exceeded water slides along the gradual slop (11) to the basin to recycle.

Abstract: A system and method for lot priority adjustment. The system includes a database, a calculation unit and an adjustment unit. The database stores at least a committed date for a lot, a throughput rate and a cycle time for respective route operations in a production line, and Work-In-Process (WIP) information of the production line. The calculation unit calculates an x-ratio for the lot on a target route operation according to a current time, the committed date and a remaining cycle time for the lot, calculates a lot weight for the lot according to current loading of a predetermined number of route operations subsequent to the target route operation, and calculates a weighted x-ratio according to the x-ratio and the lot weight. The adjustment unit adjusts a priority for the lot according to the weighted x-ratio.

Abstract: A pipeline ADC for converting an analog input signal to a digital output signal includes: a plurality of analog-to-digital converting units cascading in series to form a pipeline including a plurality of digital output ends; a calculation unit coupled to the analog-to-digital converting units for generating a plurality of calibration parameters in a first mode according to signals at the digital output ends; and a calibration unit coupled to the calculation unit and the analog-to-digital converting units for calibrating signals at the digital output ends in a second mode according to the calibration parameters, so as to generate the digital output signal.

Abstract: A computer system includes a reading device, a host computing device, an audio-and-video reproducing device, and a switching device. The reading device is operable so as to read information from a storage medium. The switching device is coupled to the reading device, the host computing device, and the audio-and-video reproducing device, and is operable in one of first and second switch states. The host computing device is operable so as to convert the information read by the reading device into audio and video output signals when the switching device is in the first switch state. The audio-and-video reproducing device is operable so as to convert the information read by the reading device into the audio and video output signals when the switching device is in the second switch state.

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.