Patents by Inventor Wen Chou

Wen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8043414
    Abstract: A method and an apparatus for desorption and a dehumidifier are provided in the present invention, in which an electrical potential is applied to electrodes disposed on both ends of an absorbing material so as to desorb the substances absorbed within the absorbing material whereby the absorbing material is capable of being maintained for cycling the absorbing operation. By means of the method and the apparatus of the present invention, the desorbing efficiency can be enhanced and the energy consumption can be reduced during desorption.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: October 25, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Shan Jeng, Ming-Shiann Shih, Jau-Chyn Huang, Yu-Li Lin, Ya-Wen Chou, Ting-Wei Huang, Yu-Ming Chang
  • Publication number: 20110226815
    Abstract: A dispensing control device for an icemaker includes a dispensing structure and a control structure assembled with the dispensing structure. The dispensing structure includes at least a first dispensing portion and a second dispensing portion for dispensing at least two kinds of materials, wherein the first and the second dispensing portion and the dispensing structure form a dispensing area in which a first position and a second position are defined respectively.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 22, 2011
    Inventor: Chin-Wen CHOU
  • Publication number: 20110223350
    Abstract: A method for producing a thermoelectric material is provided. A semiconductor material powder is provided. An electroless plating process is preformed to deposit metal nano-particles on the surface of semiconductor material powder. An electrical current activated sintering process is performed to form a thermoelectric material having one and plurality grain boundaries.
    Type: Application
    Filed: July 29, 2010
    Publication date: September 15, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Sheng Su, Chia-Hung Kuo, Ya-Wen Chou, Jie-Ren Ku, Ming-Shan Jeng, Chii-Shyang Hwang, Zong-Hao Wu
  • Patent number: 8013258
    Abstract: A shielding device for serving as an electromagnetic shield includes a shield body having a top piece and a plurality of sidewall pieces, and an electromagnetic band-gap (EBG) structure disposed on the top piece of the shield body.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: September 6, 2011
    Assignee: Mediatek Inc.
    Inventor: Wen-Chou Wu
  • Publication number: 20110205221
    Abstract: A display includes a scan line, a data line, a pixel circuit, a compensation circuit, a voltage controller, and a data line driver. The data line forms a junction with the scan line. The pixel circuit is disposed at the junction of the scan line and the data line. When the scan line and the data line are driven, the pixel circuit generates a driving current. The compensation circuit generates a comparing signal and a positioning signal based on the driving current. The voltage controller generates a reference voltage that corresponds to the positioning signal with reference to the comparing signal. The data line driver corrects an image signal based on the reference voltage, and drives the data line with the corrected image signal. A compensation circuit for the display is also disclosed.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 25, 2011
    Inventors: Chih-Lung Lin, Kuan-Wen Chou, Chun-Da Tu
  • Publication number: 20110198732
    Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 18, 2011
    Inventors: Chao-Yen LIN, Wen-Chou TSAI, Ming-Hong FANG, Jen-Yen WANG, Chih-Hao CHEN, Guo-Jyun CHIOU, Sheng-Hsiang FU
  • Publication number: 20110156281
    Abstract: The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires.
    Type: Application
    Filed: July 8, 2010
    Publication date: June 30, 2011
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Yu-Tang Pan, Shih-Wen Chou
  • Publication number: 20110133322
    Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
  • Publication number: 20110136299
    Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
  • Patent number: 7940519
    Abstract: A portable electronic apparatus including a host and a display unit pivotally connected to the host is provided. The display unit includes a panel module, a first plate having a plate body and a plurality of positioning structures provided on the plate body, and a second plate. The panel module is locked at the first plate by the positioning structures and tightly fits with the first plate. The second plate is connected to the first plate, and the panel module is held between the first plate and the second plate.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 10, 2011
    Assignee: ASUSTeK Computer Inc.
    Inventors: Wen-Chou Liu, Hsien-Tang Liao
  • Patent number: 7926541
    Abstract: A ladder drum for adjusting and regulating the angular orientation and closure of horizontal slats of a venetian blind, of the type incorporating ladder cords or tape ladders, having a polygonal profiled structure comprising a series of planar sidewalls defining a substantially hollow interior. The number of sidewalls defining the polygonal structure is greater than four sidewalls, and less than or equal to twelve sidewalls, with each adjacent plane sidewall having an internal angular orientation in the range of 90° to 150°. To enhance the uniform closure of the slats of a horizontal blind, the polygonal ladder drum is more preferably in the form of an uneven hexagon that is formed from injection molded plastics. The opposing top and bottom sidewalls are greater in dimension than the mediate sidewalls, and have attachment means to insert various widths of ladder tape. The mediate sidewalls have at least two opposing access slots to insert and retain ladder cords in a counter balanced relation.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: April 19, 2011
    Inventor: Tser Wen Chou
  • Patent number: 7921897
    Abstract: A ladder drum for adjusting and regulating the angular orientation and closure of horizontal slats of a venetian blind, of the type incorporating ladder cords or tape ladders, having a polygonal profiled structure comprising a series of planar sidewalls defining a substantially hollow interior. The number of sidewalls defining the polygonal structure is greater than four sidewalls, and less than or equal to twelve sidewalls, with each adjacent plane sidewall having an internal angular orientation in the range of 90° to 150°. To enhance the uniform closure of the slats of a horizontal blind, the polygonal ladder drum is more preferably in the form of an uneven hexagon that is formed from injection molded plastics. The opposing top and bottom sidewalls are greater in dimension than the mediate sidewalls, and have attachment means to insert various widths of ladder tape. The mediate sidewalls have at least two opposing access slots to insert and retain ladder cords in a counter balanced relation.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: April 12, 2011
    Inventor: Tser Wen Chou
  • Patent number: 7919874
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 5, 2011
    Assignees: ChipMOS Technologies, ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Patent number: 7902649
    Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: March 8, 2011
    Assignee: Chipmos Technologies Inc.
    Inventors: Chun Ying Lin, Geng Shin Shen, Yu Tang Pan, Shih Wen Chou
  • Publication number: 20110035516
    Abstract: A computer system with dual hosts is provided. The computer system includes a body, a first host, a second host and multiple peripheral devices. The first host and the second host are configured in the body, and the peripheral devices are coupled to the first host and the second host. When the first host starts, the peripheral devices are controlled by the first host. When the second host starts and the first host does not start, the peripheral devices are controlled by the second host.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Wen-Chou Liu, Chen-Wei Chiang
  • Patent number: 7884486
    Abstract: A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: February 8, 2011
    Assignee: Chipmos Technology Inc.
    Inventors: Yu-Tang Pan, Shih-Wen Chou
  • Patent number: D630086
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: January 4, 2011
    Inventor: Tser Wen Chou
  • Patent number: D636205
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: April 19, 2011
    Inventor: Tser Wen Chou
  • Patent number: D637028
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: May 3, 2011
    Inventor: Tser Wen Chou
  • Patent number: RE42349
    Abstract: A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: May 10, 2011
    Assignees: ChipMOS Technologies (Bermuda), ChipMOS Technologies Inc.
    Inventors: Chun-Hung Lin, Jesse Huang, Kuang-Hui Chen, Shih-Wen Chou