Abstract: A gas burner includes a gas valve block having a gas input control part connected to a fuel gas source and a gas output control part connected to a flame tube and gas nozzle for producing an igniting flame for burning fuel gas outputted through the flame tube, a differential pressure device adapted to control the fuel gas passage between the gas input control part and the gas output control part through a normal-close valve and a normal-open valve, an electronic igniter controlled by a cock in the gas valve block through a micro-switch to discharge sparks through discharging electrode means for burning fuel gas outputted through the gas nozzle, and a temperature switch for controlling the operation of the normal-open valve and the electronic igniter subject to a predetermined temperature range.

Abstract: The present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source. The third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.

Abstract: A method for transferring devices to a device substrate is disclosed. In one embodiment, the method includes providing an array of devices on a carrier substrate having a generally horizontal surface, where the array comprises multiple device pluralities. The method includes tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate. Each tilted device plurality is preferably in substantially the same pattern, and each tilted device plurality is placed on device regions on respective device substrates.

Abstract: An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide.

Abstract: A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.

Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.

Abstract: An improved structure of printed circuit board (PCB) under pushbutton comprises a base layer and an insulation membrane, wherein a plurality of conductive portions and corresponding contact portions are printed on the base layer and the insulation membrane respectively. A plurality of insulation portions is printed on each contact portion along its circumference; and, no glue will be applied on a corridor between every pair of the conductive potions in the base layer and the contact portions in the insulation membrane when c ombining the insulation membrane to the base layer by gluing or direct printing. By this arrangement, an air channel can be reserved for being applicable to various button groups or waterproof membrane PCBs.

Abstract: A receiving indication apparatus for E-mail located in a keyboard or mouse device for indicating E-mail being received in a computer. The apparatus includes a signal output contact located in a microprocessor installed in the keyboard and a load linked to the signal output contact. When the computer receives E-mail and notifies the microprocessor, the signal output contact immediately outputs a driving signal to actuate the load for alerting user so that user may process the E-mail immediately without the need to stare at the display screen or shut down part of the programs.

Abstract: A method of polishing a polysilicon layer by using a chemical mechanical polishing process is described. A semiconductor substrate is provided, and a shallow trench isolation structure is formed on the semiconductor substrate such that the substrate has an uneven surface. A first polysilicon layer is formed on the semiconductor substrate and the shallow trench isolation structure. A polishing step is performed on the first polysilicon layer to planarize the first polysilicon layer. A second polysilicon layer is formed on the first polysilicon layer, wherein an interface is formed between the second polysilicon layer and the first polysilicon layer.

Abstract: An instruction input device contains a baseboard having a set of pivot-jointing portions formed with two correspondent pivot holes for penetratingly disposing a shaft with a free end assembled and jointed to an instruction output switch. A flexible layer is assembled and jointed on surface of the shaft, and a coaxial force-bearing layer is further overlapped onto the flexible layer, wherein an instruction actuation switch is disposed on the baseboard at a proper position within reachable action range of the force-bearing layer. By applying the abovesaid simplified architecture, a mouse or a notebook computer with reduced weight, thickness, and size in a relatively lower cost is achievable.

Abstract: A method of fabricating a substrate having a conductive layer on opposing sides, with the conductive layers interconnected by a conductive via. The inventive method uses a dielectric substrate having a conductive layer deposited or laminated onto one or both of the substrate's opposing surfaces. For the situation of a metal layer on one side of the substrate, a laser drill is used to drill blind vias through the dielectric, stopping at the substrate/conductive layer interface. An electrolytic plating process is used to fill the via by establishing an electrical connection to the conductive layer. A second conductive layer may be deposited or laminated to the other surface of the substrate. If the starting structure has a conductive layer on both sides of the substrate, the drill is controlled to bore through the upper conductive layer at a comparatively high power and then continue at a lower power through the substrate.

Abstract: The present invention provides a method of forming a MOS transistor on a substrate of a semiconductor wafer. The method comprises forming a rectangular-shaped gate on the substrate, forming a spacer at each of two opposite sides of the gate on the substrate, performing a first ion implantation process to form a source and a drain at predetermined positions of the substrate beside the two spacers, performing a first thermal annealing process on the semiconductor wafer, removing the spacers from the two sides of the gate, performing a second ion implantation process on the substrate to form a conducting layer below each of the spacers wherein one conducting layer is electrically connected with the source and another conducting layer is electrically connected with the drain, and performing a second thermal annealing process on the semiconductor wafer for activating implants of the second ion implantation process in the two conducting layers.

Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Abstract: A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract: A power supply equipped with extractable fan deck to be applied in a computer system comprises a casing and an extractable fan set. The casing further comprises: a main frame formed by a double bending; a lateral board jointed to a lateral face of the main frame; and a rear board mounted to one end of the main frame. The extractable fan set further comprises: a sub-frame with a bent edge for jointing and defining an installation space with the rear board and a fan deck disposed in the installation space. A first fan housed in the fan deck is operated with an associated second fan located oppositely at the front end of a set of power-supply units for creating air convection to improve heat dissipation efficiency and keep the power supply under normal conditions.

Abstract: A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (VT) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the VT adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will.

Abstract: A method for forming a semiconductor structure by using super halo implant combined with offset spacer process is disclosed. This invention comprises providing a substrate with a gate electrode formed thereon and a halo implant region formed therein. Then, a dielectric layer is deposited on the substrate and the gate electrode. Next, the semiconductor structure is annealed, and the dielectric layer is anisotropically etched to form an offset spacer.

Abstract: A method for making a multilayer circuit structure using circuit substrates with apertures at edge regions is disclosed. The method includes using a roller element with teeth. The teeth are used to align the circuit substrates during a lamination process.

Abstract: A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion of the conductive layer and a portion of the barrier layer until exposing the polysilicon layer. An ion implantation is performed to form lightly doped regions in the substrate using the remaining conductive layer and the remaining barrier layer as a mask. A spacer is formed on the side-wall of the conductive layer and on the side-wall of the barrier layer. The polysilicon layer and the gate oxide layer, which are in positions other than those of the remaining conductive layer and the spacer, are removed. The remaining conductive layer and the remaining polysilicon layer constitute a gate with an inversed, T-shaped cross-section.

Abstract: A method for forming borderless contact capable of reducing junction leakage current by forming a deep junction in the source/drain region nearest the borderless contact to eliminate most of the leakage current. The method includes the steps of first forming a shallow trench isolation structure for isolating devices in a semiconductor substrate. In the subsequent step, an ion implantation is carried out implanting ions at a small tilt angle to form source/drain regions such that source/drain region nearest to the shallow trench isolation structure has a deep junction. Finally, a borderless opening is formed above the source/drain region and the shallow trench isolation structure, and then conductive material is deposited into the borderless opening to form the borderless contact.