Patents by Inventor Wen Chu

Wen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200235747
    Abstract: An analog-to-digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjusting circuitry. The ADC circuitries convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuitry performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuitry analyzes time difference information within even-numbered sampling periods of the clock signals, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 23, 2020
    Inventors: Wen-Juh KANG, Yu-Chu CHEN, Man-Pio LAM
  • Publication number: 20200222498
    Abstract: The present disclosure provides various molecular constructs having a plurality of fatty acids and a functional element. Methods for treating various diseases using such molecular constructs are also disclosed.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 16, 2020
    Applicant: Immunwork Inc.
    Inventors: Tse-Wen CHANG, Hsing-Mao CHU, Chien-Jen LIN
  • Patent number: 10715924
    Abstract: A MEMS microphone includes a backplate that has a plurality of open areas, and a diaphragm spaced apart from the backplate. The diaphragm is deformable by sound waves to cause gaps between the backplate and the diaphragm being changed at multiple locations on the diaphragm. The diaphragm includes a plurality of anchor areas, located near a boundary of the diaphragm, which is fixed relative to the backplate. The diaphragm also includes multiple vent valves. Examples of the vent valve include a wing vent valve and a vortex vent valve.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Chun Yin Tsai
  • Patent number: 10707260
    Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 7, 2020
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu
  • Publication number: 20200213701
    Abstract: An integrated microphone device is provided. The integrated microphone device includes a substrate, a plate, and a membrane. The substrate includes an aperture allowing acoustic pressure to pass through. The plate is disposed on a side of the substrate. The membrane is disposed between the substrate and the plate and movable relative to the plate as acoustic pressure strikes the membrane. The membrane includes a vent valve having an open area that is variable in response to a change in acoustic pressure.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Chun-Wen CHENG, Chia-Hua CHU, Chun-Yin TSAI, Tzu-Heng WU, Wen-Cheng KUO
  • Patent number: 10689247
    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • Publication number: 20200190605
    Abstract: The invention relates to a detective molecule, and more particularly to a detective molecule and a kit for detecting a target molecule, a method for predicting fragrance production in an orchid, and a method for breeding a scented orchid.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: HONG-HWA CHEN, YU-CHEN CHUANG, WEN-CHIEH TSAI, YI-CHU HUNG, WEN-HUEI CHEN, CHI-YU HSU, CHUAN-MING YEH, NOBUTAKA MITSUDA, MASARU OHME-TAKAGI
  • Publication number: 20200192225
    Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 18, 2020
    Inventors: Ming-Hsuan CHUANG, Po-Sheng LU, Shou-Wen KUO, Cheng-Yi HUANG, Chia-Hung CHU
  • Publication number: 20200190529
    Abstract: The invention relates to a nucleic acid molecule that improves aroma production in an orchid, and a cell and a transgenic orchid comprising the nucleic acid molecule. The invention further relates to a polypeptide that improves aroma production in an orchid, and a method for improving the production of aroma in an orchid.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: HONG-HWA CHEN, YU-CHEN CHUANG, WEN-CHIEH TSAI, YI-CHU HUNG, WEN-HUEI CHEN
  • Publication number: 20200190518
    Abstract: A series of peptides and a peptide-siRNA complex are disclosed, wherein the peptide based complex effectively enhances delivery of siRNA molecules into the cells and release of siRNA in the cell, and improves siRNA mediated gene silencing efficiency of cellular targets. Pharmaceutical compositions that include the complex, as well as a use of the complex in the gene therapy field, are also disclosed.
    Type: Application
    Filed: January 24, 2020
    Publication date: June 18, 2020
    Inventors: Pu Chen, Dafeng CHU, Baoling CHEN, Wen XU, Ran PAN
  • Patent number: 10686047
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Publication number: 20200185124
    Abstract: A high-speed flat cable having a better bending/folding memory and a manufacturing method thereof are provided. The high-speed flat cable includes a plurality of shielded signal units, one or more bendable composite layers, and an adhesive layer. The shielded signal units are substantially coplanar, spaced apart from each other or adjoining each other. The one or more bendable composite layers includes an inner insulating film layer, a bendable aluminum foil layer, and an outer insulating film layer. The one or more bendable composite layers composed of the inner insulating film layer, the bendable aluminum foil layer, and the outer insulating film layer increase its mechanical bending/folding property to improve the bending/folding memory. The one or more bendable composite layers allow the flat cable to be bent with ease without rebounding, thereby enhancing production efficiency.
    Type: Application
    Filed: November 14, 2017
    Publication date: June 11, 2020
    Applicant: Amphenol Assemble Tech Co., Ltd
    Inventors: Wen Chu Yang, Zhi Ming Huang, David Rosenboom, Jesse Jaramillo
  • Patent number: 10680019
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Publication number: 20200175518
    Abstract: An apparatus (100) for real-time detection of fraudulent digital transactions is disclosed. The apparatus comprises: a transceiver module arranged to receive information data of a digital transaction; a model generator module (102) arranged to dynamically generate a predictive model for fraud detection based collectively on historical information data relating to identified fraudulent transactions and the received information data; and a fraud detection module (104) having a plurality of anomaly detection modules (1042, 1044, 1046) arranged to respectively process the received information data differently to generate a plurality of scores, which are aggregated to provide an aggregated score to enable real-time determination of whether the digital transaction is a fraudulent digital transaction. A first anomaly detection module (1042) is configured to process the received information data using the predictive model to generate a first score. A related method is disclosed too.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 4, 2020
    Applicant: Jewel Paymentech Pte Ltd
    Inventors: Benjamin Min Xian CHU, Jer-Wei LAM, Jeanette Yi Wen TAN, Azim Adil YAZDANI
  • Publication number: 20200176319
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.
    Type: Application
    Filed: June 3, 2019
    Publication date: June 4, 2020
    Inventors: Che-Yu Lin, Chien-Wei Lee, Chien-Hung Chen, Wen-Chu Hsiao, Yee-Chia Yeo
  • Publication number: 20200176395
    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Patent number: 10668165
    Abstract: The present disclosure provides various molecular constructs having a targeting element and an effector element. Methods for treating various diseases using such molecular constructs are also disclosed.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: June 2, 2020
    Assignee: IMMUNWORK INC.
    Inventors: Tse-Wen Chang, Chien-Jen Lin, Hsing-Mao Chu
  • Patent number: 10673482
    Abstract: A signal transmission device includes a transceiver circuitry and a control circuitry. The transceiver circuitry is configured to receive first device data from an external device through a channel. The control circuitry is configured to calculate a least one system parameter of the transceiver circuitry based on the first device data, second device data associated with the transceiver circuitry, and at least one requirement of a predetermined communication protocol, in order to link with the external device.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 2, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Hua-Shih Liao
  • Patent number: 10673304
    Abstract: A speed reducing device includes a motor and a speed reducing mechanism. The motor includes a stator portion and a rotor portion. The rotor portion includes a first eccentric ring and a second eccentric ring. The speed reducing mechanism is partially accommodated within the rotor portion. The speed reducing mechanism includes a first roller assembly, a second roller assembly, a third roller assembly, a first cycloid disc set and a second cycloid disc set. The first roller assembly includes at least one first roller. The second roller assembly includes at least one second roller. The third roller assembly includes an output shaft and at least one third roller. The first cycloid disc set is mounted around the output shaft and disposed within the first eccentric ring. The second cycloid disc set is mounted around the output shaft and disposed within the second eccentric ring.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 2, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ching-Hsiung Tsai, Chi-Wen Chung, En-Yi Chu
  • Patent number: D885379
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 26, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chun-Wen Wang, Wang-Hung Yeh, Hsin-Chieh Fang, Che-Hsien Lin, Shu-Hung Lin, Che-Hsien Chu