Patents by Inventor Wen Chu

Wen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343858
    Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 26, 2023
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Publication number: 20230276928
    Abstract: The invention provides a protable article device, which mainly comprises a flat, expandable sheath and a binding component. The inner surface of the sheath is flexible, with a non-slip surface with plurality grooves; it is connected to the Velcro and positioning ring of the binding component. This design enables objects to be tightly fastened inside the sheath because of the elasticity of the Velcro. The positioning ring of the sheath can be locked to a clip holder to enable easy carrying and retrieval when outdoors.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 7, 2023
    Inventor: Chi-Wen CHU
  • Patent number: 11748856
    Abstract: A method for detecting defects in a near-eye display is provided. The method includes the following steps: obtaining a reference image and a DUT image according to a first image and a second image captured by a camera through a Fresnel lens when a display panel respectively displays a test-pattern image and a test-background image; performing a fast Fourier transform on the reference image and the DUT image to obtain a frequency-domain reference image and a frequency-domain DUT image; calculating an average value of pixel values above a predetermined cut-off ratio in a histogram of each first region of interest (ROI) in a filtered frequency-domain reference image as a corresponding threshold; comparing each pixel in the filtered DUT image with the corresponding threshold to generate a determination result; and building a defective-status map of the near-eye display according to the determination results.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 5, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yeh Lin, Wen-Chu Yang, Chi-Hsien Yang
  • Patent number: 11721745
    Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Publication number: 20230223335
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: March 7, 2023
    Publication date: July 13, 2023
    Inventors: Hung Hsun LIN, Wei-Chun HUA, Wen-Chu HUANG, Yen-Yu CHEN, Che-Chih HSU, Chinyu SU, Wen Han HUNG
  • Publication number: 20230113464
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure, and a source/drain structure in the fin structure and adjacent to the gate structure. The source/drain structure includes: a first epitaxial layer over the fin structure, a second epitaxial layer over the first epitaxial layer, and an epitaxial capping layer over the second epitaxial layer. The semiconductor structure also includes a silicide layer formed in contact with the source/drain structure. The silicide layer has a curved bottom surface, and the curved bottom surface of the silicide layer intersects with the second epitaxial layer and the epitaxial capping layer.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu LI, Wei-Yang LEE, Wen-Chu HSIAO
  • Publication number: 20230103483
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: Che-Yu Lin, Chien-Wei Lee, Chien-Hung Chen, Wen-Chu Hsiao, Yee-Chia Yeo
  • Publication number: 20230100778
    Abstract: Disclosed herein is a method for promoting growth of a probiotic microorganism. The method includes cultivating the probiotic microorganism in a growth medium containing a fermented culture of lactic acid bacterial strains that include Lactobacillus salivarius subsp. salicinius AP-32 deposited at the China Center for Type Culture Collection (CCTCC) under CCTCC M 2011127, Lactobacillus plantarum LPL28 deposited at the China General Microbiological Culture Collection Center (CGMCC) under CGMCC 17954, Lactobacillus acidophilus TYCA06 deposited at the CGMCC under CGMCC 15210, and Bifidobacterium longum subsp. infantis BLI-02 deposited at the CGMCC under CGMCC 15212.
    Type: Application
    Filed: April 19, 2022
    Publication date: March 30, 2023
    Inventors: Hsieh-Hsun HO, Ching-Wei CHEN, Yu-Fen HUANG, Cheng-Chi LIN, Chen-Hung HSU, Tsai-Hsuan YI, Yu-Wen CHU, Yi-Wei KUO, Jui-Fen CHEN, Shin-Yu TSAI
  • Patent number: 11616013
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20230086405
    Abstract: Formulations with enhanced SN-38 solubility and oral absorption. In one embodiment, a formulation or a pharmaceutical composition comprises (a) 7-Ethyl-10-hydroxy-camptothecin (SN-38); and (b) a mixture of pharmaceutically acceptable excipients comprising (i) N-Methylpyrrolidone; and (ii) Vitamin E TPGS or a copolymer, the copolymer being 50/50 poly(lactic-co-glycolic acid), or 75/25 poly(lactic-co-glycolic acid) (PLGA); with the provision that if the VitE TPGS is present, the mixture of the excipients further comprises a polymer selected from the group consisting of Hydroxypropyl cellulose, Hydroxypropyl methylcellulose, VP/VAc copolymer 60/40, poloxamer 407, and Lauroyl Macrogol-32 glycerides; wherein the pharmaceutical composition contains no water, is in a liquid or a gel form, and the SN-38 is dissolved in the mixture of the excipients without precipitation.
    Type: Application
    Filed: August 5, 2022
    Publication date: March 23, 2023
    Inventors: Yi-Wen CHU, Du-Shieng CHIEN
  • Patent number: 11532749
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Mu Li, Wei-Yang Lee, Wen-Chu Hsiao
  • Publication number: 20220399234
    Abstract: A method of semiconductor die singulation is provided. The method includes forming a first trench along a singulation lane of a semiconductor wafer. A second trench is formed extending from a bottom of the first trench. A portion of the semiconductor wafer remains between a bottom of the second trench and a backside of the semiconductor wafer. A cut is formed by way of a laser to singulate die of the semiconductor wafer. The cut extends through the portion of the semiconductor wafer remaining between the bottom of the second trench and the backside of the semiconductor wafer.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 15, 2022
    Inventors: WeiCheng Chuang, PaoTung Pan, Che Lun Cheng, Yao Jung Chang, Yu-Wen Chu, Chun-Hui Lee, Che-Kai Hsu, Kuan Lin Huang
  • Patent number: 11527442
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu Lin, Chien-Wei Lee, Chien-Hung Chen, Wen-Chu Hsiao, Yee-Chia Yeo
  • Publication number: 20220371193
    Abstract: Systems, apparatus, and methods are described for robotic learning and execution of skills. A robotic apparatus can include a memory, a processor, sensors, and one or more movable components (e.g., a manipulating element and/or a transport element). The processor can be operatively coupled to the memory, the movable elements, and the sensors, and configured to obtain information of an environment, including one or more objects located within the environment. In some embodiments, the processor can be configured to learn skills through demonstration, exploration, user inputs, etc. In some embodiments, the processor can be configured to execute skills and/or arbitrate between different behaviors and/or actions. In some embodiments, the processor can be configured to learn an environmental constraint. In some embodiments, the processor can be configured to learn using a general model of a skill.
    Type: Application
    Filed: March 9, 2022
    Publication date: November 24, 2022
    Inventors: Vivian Yaw-Wen CHU, Shuai LI, Forrest GREEN, Peter WORSNOP, Andrea Lockerd THOMAZ
  • Publication number: 20220367343
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Patent number: 11461878
    Abstract: A method for eliminating a ring effect is provided. The method includes: capturing, by a camera, a standard ring image generated by light illuminating a standard Fresnel lens; establishing a compensation lookup table according to the standard ring image and obtaining a standard ring center point; capturing, by the camera, a ring image generated by the light illuminating a Fresnel lens to be tested; obtaining a ring center point according to the ring image; obtaining a conversion relationship between the ring center point and the standard ring center point; and performing a compensation procedure on the ring image according to the compensation lookup table and the conversion relationship to eliminate the ring effect in the ring image.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 4, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yeh Lin, Wen-Chu Yang, Chi-Hsien Yang
  • Publication number: 20220238709
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
  • Publication number: 20220206294
    Abstract: A head-mounted eye tracking system including an optical combiner, an eye tracker and a signal processor is provided. The optical combiner includes an optical coupler. The eye tracker is at least partially disposed on the optical combiner and is suitable for sensing an eyeball movement of a wearer. The eye tracker includes a plurality of light-emitting devices and a plurality of sensing devices. The plurality of light-emitting devices are suitable for emitting tracking beams. The plurality of sensing devices are suitable for receiving the tracking beams reflected by the eyeball of the wearer. The signal processor is signally connected to the eye tracker.
    Type: Application
    Filed: April 13, 2021
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Jhih Luo, Chia-Hsin Chao, Chun-Wen Chu, Ching-Ya Yeh
  • Publication number: 20220207664
    Abstract: A method for detecting defects in a near-eye display is provided. The method includes the following steps: obtaining a reference image and a DUT image according to a first image and a second image captured by a camera through a Fresnel lens when a display panel respectively displays a test-pattern image and a test-background image; performing a fast Fourier transform on the reference image and the DUT image to obtain a frequency-domain reference image and a frequency-domain DUT image; calculating an average value of pixel values above a predetermined cut-off ratio in a histogram of each first region of interest (ROI) in a filtered frequency-domain reference image as a corresponding threshold; comparing each pixel in the filtered DUT image with the corresponding threshold to generate a determination result; and building a defective-status map of the near-eye display according to the determination results.
    Type: Application
    Filed: March 29, 2021
    Publication date: June 30, 2022
    Inventors: Yeh LIN, Wen-Chu YANG, Chi-Hsien YANG
  • Patent number: 11309418
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Liang-Yi Chen, Wen-Chu Hsiao